M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 468

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
22.11 CAN Module
e
E
1
. v
J
Table 22.2 CAN Module Status Updating Period
6
0
(Example 1) Condition X
(Example 2) Condition X
(Example 3) Condition X
(Example 4) Condition X
(Example 5) Condition X
22.11.1 Reading C0STR Register
C
1
9
1 .
B
2 /
The CAN module on the M16C/29 Group updates the status of the C0STR register in a certain period.
When the CPU and the CAN module access to the C0STR register at the same time, the CPU has the
access priority; the access from the CAN module is disabled. Consequently, when the updating period of
the CAN module matches the access period from the CPU, the status of the CAN module cannot be
updated. (See Figure 22.5)
Accordingly, be careful about the following points so that the access period from the CPU should not
match the updating period of the CAN module:
(1) There should be a wait time of 3f
(2) When the CPU polls the C0STR register, the polling period must be 3f
0
2
9
1
3f
M
22.7)
0
G
register. (See Figure 22.6)
CAN
1
r a
o r
0 -
3 .
1
u
period = 3
, 0
1
p
2
2
0
0
7
page 442
X
IN
IN
IN
IN
IN
IN
(Original oscillation period)
16 MHz CCLK: Divided by 1
16 MHz CCLK: Divided by 2
16 MHz CCLK: Divided by 4
16 MHz CCLK: Divided by 8
16 MHz CCLK: Divided by 16
f o
4
5
8
CAN
or longer (see Table 22.2) before the CPU reads the C0STR
Division value of the CAN clock (CCLK)
3f
3f
3f
3f
3f
CAN
CAN
CAN
CAN
CAN
period = 3
period = 3
period = 3
period = 3
period = 3
CAN
or longer. (See Figure
62.5 ns
62.5 ns
62.5 ns
62.5 ns
62.5 ns
1 = 187.5 ns
2 = 375 ns
4 = 750 ns
8 = 1.5 s
16 = 3 s
22. Usage Notes