MC68HC11K1CFUE3 Freescale Semiconductor, MC68HC11K1CFUE3 Datasheet - Page 121

• Manufacturer Part Number: MC68HC11K1CFUE3
• Description: MCU 8-BIT 768 RAM 3MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K1CFUE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.5.1.3 Software Interrupt (SWI)
5.5.2 Maskable Interrupts
M68HC11K Family
MOTOROLA
Address: $0039
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in
execution of the illegal opcode, which can lead to stack overflow, the
service routine should reinitialize the stack pointer.
SWI cannot be masked by virtue of the fact that it is a software
instruction. It is not inhibited by the global mask bits in the CCR.
Execution of SWI sets the I mask bit, so other interrupts are inhibited
until user software clears the I bit or SWI terminates with an RTI
instruction.
All maskable interrupts are generated by on-chip peripherals, with the
exception of the IRQ pin. This input can be connected through a
wired-OR network to external devices. When one of these devices pulls
IRQ low, a software accessible interrupt flag is set. When enabled, this
flag causes a constant request for interrupt service. After the flag is
cleared, the service request is released. IRQ is low-level sensitive by
default, but can be set for falling-edge sensitivity by the IRQE bit in the
OPTION register (see
IRQE — Configure IRQ for Edge-Sensitive Operation Bit
Reset:
Read:
Write:
special modes
Figure 5-6. System Configuration Options Register (OPTION)
This bit can be written only once during the first 64 E-clock cycles after
reset in normal modes.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Low-level recognition
1 = Falling-edge recognition
ADPU
Bit 7
0
Go to: www.freescale.com
Resets and Interrupts
CSEL
6
0
Figure
IRQE
5
0
(1)
5-6).
DLY
4
1
(1)
CME
3
0
FCME
2
0
(1)
Resets and Interrupts
CR1
1
0
Technical Data
(1)
Interrupts
CR0
Bit 0
0
(1)
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