MC68HC11K1CFUE3 Freescale Semiconductor, MC68HC11K1CFUE3 Datasheet - Page 54

• Manufacturer Part Number: MC68HC11K1CFUE3
• Description: MCU 8-BIT 768 RAM 3MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K1CFUE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Central Processor Unit (CPU)
3.6.1 Immediate
3.6.2 Direct
3.6.3 Extended
3.6.4 Indexed
Technical Data
54
In the immediate addressing mode, the byte(s) immediately following the
opcode contain the arguments. The number of bytes following the
opcode matches the size of the register or memory location being used.
Immediate instructions can be two, three, or (if a prebyte is required) four
bytes.
In the direct addressing mode, the user specifies only the low-order byte
of the effective address in a single byte following the opcode. The
processor assumes the high-order byte of the address to be $00. Thus,
the CPU accesses addresses $00–$FF directly, using 2-byte
instructions. This reduces execution time by eliminating the additional
memory access required for the high-order address byte. Most
applications reserve this 256-byte area for frequently referenced data,
but various combinations of internal registers, RAM, or external memory
can occupy these addresses.
In the extended addressing mode, the two bytes following the opcode
byte contain the effective address of the argument. For this reason,
instructions are three bytes, or they are four bytes if a prebyte is
required.
In the indexed addressing mode, the CPU computes the effective
address of the argument by adding an 8-bit unsigned offset to the value
contained in an index register (IX or IY). Any memory location in the
64-Kbyte address space can be accessed with this mode. The
instructions are from two to five bytes.
Freescale Semiconductor, Inc.
For More Information On This Product,
Central Processor Unit (CPU)
Go to: www.freescale.com
M68HC11K Family
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