MC68HC11K1CFUE3 Freescale Semiconductor, MC68HC11K1CFUE3 Datasheet - Page 131

• Manufacturer Part Number: MC68HC11K1CFUE3
• Description: MCU 8-BIT 768 RAM 3MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K1CFUE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

M68HC11K Family
MOTOROLA
Address: $0039
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in
to restart the system, a normal reset sequence results and all pins and
registers are reinitialized.
To use the IRQ pin as a means of recovering from STOP, the I bit in the
CCR must be clear (IRQ not masked). The XIRQ pin can be used to
wake up the MCU from STOP regardless of the state of the X bit in the
CCR, although the state of this bit does affect the recovery sequence. If
X is clear (XIRQ not masked), the MCU executes a normal XIRQ service
routine. If X is set (XIRQ masked or inhibited), then processing continues
with the instruction that immediately follows the STOP instruction, and
no XIRQ interrupt service is requested or pending.
Executing a STOP instruction requires special consideration when the
clock monitor is enabled. Because the stop function halts all clocks, the
clock monitor function will generate a reset sequence if it is enabled at
the time the stop mode was initiated. To prevent this, clear the CME and
FCME bits in the OPTION register before executing a STOP instruction
to disable the clock monitor. After recovery from STOP, set the CME bit
to enable the clock monitor.
Systems using the internal oscillator require a delay after restart upon
leaving STOP to allow the oscillator to stabilize. If a stable external
oscillator is used, the DLY control bit in the OPTION register can be used
to bypass this startup delay (see
control bit; it can be cleared during initialization. Do not use reset to
recover from STOP if the DLY is to be bypassed, since reset sets the
DLY bit again, causing the restart delay. This same delay will follow a
power-on reset, regardless of the state of the DLY control bit, but does
not apply to a reset while the clocks are running.
Reset:
Read:
Figure 5-11. System Configuration Options Register (OPTION)
Write:
special modes
Freescale Semiconductor, Inc.
For More Information On This Product,
ADPLE
Bit 7
0
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Resets and Interrupts
DSEL
6
0
IRQE
5
0
(1)
DLY
Figure
4
1
(1)
5-11). Reset sets the DLY
CME
3
0
FCME
2
0
(1)
Low-Power Operation
Resets and Interrupts
CR1
1
0
Technical Data
(1)
CR0
Bit 0
0
(1)
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