HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 489

• Manufacturer Part Number: HD64F7145F50
• Description: IC SUPERH MCU FLASH 256K FP144F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7145F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.6
Figure 13.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. Data is
transferred in 8-bit units. In clocked synchronous serial communication, data on the transmission
line is output from one falling edge of the serial clock to the next. In clocked synchronous mode,
the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is
output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or
multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication by use of a common clock. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer.
13.6.1
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and
CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed, the clock is fixed high. However, during receive-only operation the
synchronization clock is output until an overrun error occurs or the RE bit is cleared to 0. When
receive operation in single-character units is desired, select an external clock as the clock source.
Figure 13.14 Data Format in Clocked Synchronous Communication (For LSB-First)
Operation in Clocked Synchronous Mode
Clock
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Don’t care
*
LSB
Bit 0
One unit of transfer data (character or frame)
Bit 1
Bit 2
Bit 3
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 443 of 882
Bit 4
Bit 5
Bit 6
MSB
Bit 7
REJ09B0108-0400
Don’t care
*