DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 288

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.7.5
When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the CS5 pin.
When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2,
SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous
DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ
and SDRAMφ. When the frequency multiplication factor of the PLL circuit is ×4, the phase of
SDRAMφ and that of φ are the same.
When the CLK pin of the synchronous DRAM is directly connected to SDRAMφ of this LSI, it is
recommended to set the frequency multiplication factor of the PLL circuit to ×1 or ×2.
Note: SDRAMφ output timing is shown when the frequency multiplication factor of the PLL
6.7.6
The four states of the basic timing consist of one T
output cycle) state, and the T
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.44 shows the basic timing for synchronous DRAM.
Rev.7.00 Mar. 18, 2009 page 220 of 1136
REJ09B0109-0700
Figure 6.43 Relationship between φ and SDRAMφ (when PLL Frequency Multiplication
circuit is ×1 or ×2.
Synchronous DRAM Clock
Basic Timing
SDRAMφ
φ
c1
and two T
Factor Is ×1 or ×2)
c2
(column address output cycle) states.
T cyc
p
(precharge cycle) state, one T
1/4 T cyc (90°)
r
(row address