DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 560

IC H8S MCU FLASH 512K 144LQFP

DF2378RVFQ34V

Manufacturer Part Number
DF2378RVFQ34V
Description
IC H8S MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2378RVFQ34V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 I/O Ports
10.5.3
PORT5 shows the pin states. PORT5 cannot be modified.
Bit
7to 4 ⎯
3
2
1
0
Note:
10.5.4
Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, and interrupt inputs. The
correspondence between the register specification and the pin functions is shown below.
• P53/ADTRG/IRQ3
P53DDR
Pin function
Notes: 1. ADTRG input when TRGS1 = TRGS0 = 1.
Rev.7.00 Mar. 18, 2009 page 492 of 1136
REJ09B0109-0700
The pin function is switched as shown below according to the combination of bits TRGS1 and
TRGS0 in the A/D control register (ADCR), bit ITS3 in ITSR, and bit P53DDR.
Bit Name
P53
P52
P51
P50
* Determined by the states of pins P53 to P50.
2. IRQ3 input when ITS3 = 0.
Port 5 Register (PORT5)
Pin Functions
Initial Value
Undefined
⎯*
⎯*
⎯*
⎯*
P53 input
R/W
R
R
R
R
R
0
Description
Reserved
Undefined values are read from these bits.
If bits P53 to P50 are read while P5DDR bits are set
to 1, the P5DR values are read. If a port 5 read is
performed while P5DDR bits are cleared to 0, the
pin states are read.
IRQ3 interrupt input *
ADTRG input *
1
2
P53 output
1

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