DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 603

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.15
Port G is a 7-bit I/O port that also has other functions. The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
• Port Function Control Register 0 (PFCR0)
10.15.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G.
PGDDR cannot be read; if it is, an undefined value will be read.
Bit
7
6
5
4
3
2
1
0
Note:
Bit Name
⎯
PG6DDR
PG5DDR
PG4DDR
PG3DDR
PG2DDR
PG1DDR
PG0DDR
* PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.
Port G
Initial Value
0
0
0
0
0
0
0
1/0 *
R/W
⎯
W
W
W
W
W
W
W
Description
Reserved
•
•
Modes 7 (when EXPE = 1), 1, 2, and 4
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ)
when the appropriate bus controller settings are
made. Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS output
pins when the corresponding PGDDR bit is set to 1,
and as input ports when the bit is cleared to 0.
When CS3E to CS0E are cleared to 0, pins PG3 to
PG0 are I/O ports, and their functions can be
switched with PGDDR.
Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Rev.7.00 Mar. 18, 2009 page 535 of 1136
Section 10 I/O Ports
REJ09B0109-0700