MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 263
![IC MCU 33MHZ 128K FLASH 144-LQFP](/photos/12/42/124277/mmc2107cfcag33_sml.jpg)
MMC2107CFCAG33
Manufacturer Part Number
MMC2107CFCAG33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2107
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
72
Number Of Timers
2
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Cpu Family
Mcore
Device Core
MCORE
Device Core Size
32b
Frequency (max)
33MHz
Total Internal Ram Size
8KB
# I/os (max)
72
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
3.6/5.5V
Operating Supply Voltage (min)
2.7/4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2107CFCAG33
Manufacturer:
FREESCALE
Quantity:
210
Company:
Part Number:
MMC2107CFCAG33
Manufacturer:
freescaie
Quantity:
35
Company:
Part Number:
MMC2107CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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12.3.2 Stop Mode
12.4 Interrupt/General-Purpose I/O Pin Descriptions
12.5 Memory Map and Registers
12.5.1 Memory Map
MMC2107 – Rev. 2.0
MOTOROLA
0x00c6_0000
0x00c6_0002
0x00c6_0004
0x00c6_0006
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Writing to reserved address locations has no effect, and reading returns 0s.
Address
only addresses have no effect and result in a cycle termination transfer error.
NOTE:
EPORT data direction register (EPDDR)
EPORT data register (EPDR)
EPORT flag register (EPFR)
In stop mode, there are no clocks available to perform the edge-detect
function. Only the level-detect logic is active (if configured) to allow any
low level on the external interrupt pin to generate an interrupt (if enabled)
to exit stop mode.
The input pin synchronizer is bypassed for the level-detect logic since no
clocks are available.
All pins default to general-purpose input pins at reset. The pin value is
synchronized to the rising edge of CLKOUT when read from the EPORT
pin data register (EPPDR). The values used in the edge/level detect
logic are also synchronized to the rising edge of CLKOUT. These pins
use Schmitt triggered input buffers which have built in hysteresis
designed to decrease the probability of generating false edge-triggered
interrupts for slow rising and falling input signals.
This subsection describes the memory map and register structure.
Refer to
EPORT has a base address of 0x00c6_0000.
Table 12-1. Edge Port Module Memory Map
Freescale Semiconductor, Inc.
Bits 15–8
For More Information On This Product,
Table 12-1
EPORT pin assignment register (EPPAR)
Edge Port Module (EPORT)
Go to: www.freescale.com
for a description of the EPORT memory map. The
EPORT interrupt enable register (EPIER)
EPORT pin data register (EPPDR)
Interrupt/General-Purpose I/O Pin Descriptions
Reserved
Bits 7–0
(2)
Edge Port Module (EPORT)
Technical Data
Access
S/U
S/U
S
S
(1)
263
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