DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 184

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 4 Exception Handling
4.3.2
When the RES or MRES pin goes low, this LSI enters the reset. To ensure that this LSI is reset,
hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the
RES or MRES pin low for at least 20 states. When the RES or MRES pin goes high after being
held low for the necessary time, this LSI starts reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Figures 4.1 shows an example of the reset sequence.
Rev. 6.00 Mar. 18, 2010 Page 122 of 982
REJ09B0054-0600
initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1.
execution starts from the address indicated by the PC.
Reset Exception Handling
(1)(3) Reset exception handling vector address (at power on reset, (1) = H'000000, (3) = H'000002,
(2)(4) Start address (contents of reset exception handling vector address)
(5)
(6)
Note:
Address bus
RD
HWR, LWR
D15 to D0
φ
RES, MRES
Start address ((5) = (2) (4))
First program instruction
at manual reset, (1) = H'000004, (3) = H'000006)
*
Three states are inserted for waiting.
Figure 4.1 Reset Sequence (Mode 4)
(1)
*
Vector fetch
(2)
High
*
(3)
(4)
processing
Internal
program instruction
Prefetch of first
*
(5)
(6)