DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 595

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

14.4.3
This section shows an example of performing a master reception using the DTC after slave
reception.
(1) IEB Initialization
(a) Setting the IEBus Control Register (IECTR)
(b) Setting the IEBus Master Unit Address Registers 1 and 2 (IEAR1 and IEAR2)
RE, DEE
IERSR
IECTR
IEFLG
IEFLG
RxRDY
IEMA1
IEMA2
Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Set the
RE bit to 1 to perform reception. The LUEE bit does not need to be specified.
Specify the master unit address and specify the communications mode in IEAR1. Compare
with the slave address in the communications frame and receive the frame if matched.
MRQ
CMX
SRQ
RSS
SRE
RxS
RxF
RxE
Slave reception
Master Reception
Figure 14.10 Error Occurrence in the Broadcast Reception (DEE = 1)
H: Header, MA: Master address field, SA: Slave address field,
CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field
Dn
Broadcast reception is performed while the DEE bit is set to 1.
H
MA
Set the RxE flag and the master unit address in IEMA1 and IEMA2.
SA
CF
The RxRDY flag has not been cleared when the control field is received.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Broadcast reception
LF
Lower 4 bits of the master address
Upper 8 bits of the master address
D1
D2
Rev. 6.00 Mar. 18, 2010 Page 533 of 982
Dn-1
Dn
REJ09B0054-0600