DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 456
![MCU 3V 384K I-TEMP 100-TQFP](/photos/28/61/286119/100-tqfp_series__ptqp0100lc-a_sml.jpg)
DF2239TF16I
Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2239TF16I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
HD64F2239TF16I
- Current page: 456 of 1048
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Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 394 of 982
REJ09B0054-0600
Bit
3
2
Bit Name
TGFD
TGFC
Initial value
0
0
R/W
R/(W) *
R/(W) *
1
1
Description
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and
3 *
In channels 1, 2, 4 *
always read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and
3 *
In channels 1, 2, 4 *
always read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
3
3
.
.
When TCNT = TGRD while TGRD is functioning
as output compare register
When TCNT value is transferred to TGRD by
input capture signal while TGRD is functioning
as input capture register
When DTC is activated by TGID interrupt while
DISEL bit of MRB in DTC is 0 with the transfer
counter not being 0
When 0 is written to TGFD after reading TGFD
= 1
When TCNT = TGRC while TGRC is functioning
as output compare register
When TCNT value is transferred to TGRC by
input capture signal while TGRC is functioning
as input capture register
When DTC is activated by TGIC interrupt while
DISEL bit of MRB in DTC is 0 with the transfer
counter not being 0
When 0 is written to TGFC after reading TGFC
= 1
3
3
, and 5 *
, and 5 *
3
3
, bit 3 is reserved. It is
, bit 2 is reserved. It is
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