HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 261

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.1
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and timing in the
case of instruction fetch.
8.1.1
The UBC has the following features:
• The following break comparison conditions can be set.
• User break is generated upon satisfying break conditions. A user-designed user-break
• In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and, then channel B match with logical AND, but
not in the same bus cycle).
⎯ Address (Compares 40 bits comprised of a 32-bit logical address prefixed with an ASID
⎯ Data (only on channel B, 32-bit maskable)
⎯ Bus master: CPU cycle or DMAC cycle
⎯ Bus cycle: instruction fetch or data access
⎯ Read/write
⎯ Operand size: byte, word, or longword
condition exception processing routine can be run.
is executed.
address
Comparison bits are maskable in 32-bit units, user can easily program it to mask addresses
at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc.
The 8-bit ASID checking is from MMU control to indicate hit or not hit.)
One of four address buses (CPU address bus (LAB), cache address bus (IAB),
X-memory address bus (XAB) and Y-memory address bus (YAB)) can be selected.
One of the four data buses (CPU data bus (LDB), cache data bus (IDB), X-memory data
bus (XDB) and Y-memory data bus (YDB)) can be selected.
Overview
Features
Section 8 User Break Controller
Rev.6.00 Mar. 27, 2009 Page 203 of 1036
Section 8 User Break Controller
REJ09B0254-0600