HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 712

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial IO (SIOF)
20.4.1
Notes
When using SIOF, the following phenomenon may occur.
(1) During SIOF transmit with DMA transferring, SIOF may suddenly stop internal DMA transfer
(2) During SIOF transmit and transmit FIFO empty, underflow or overflow, some data transmit
(3) During SIOF receive operation with DMA internal peripheral module request mode, some data
(4) During receive operation, some receive data may fail when a write occurs at reading from
(5) During SIOF receive operation and receive FIFO empty, underflow or overflow, some data
Countermeasures
Countermeasures to deal with software using SIOF.
(1) Notes (1) and (2)
(2) Notes (3), (4), and (5)
Rev.6.00 Mar. 27, 2009 Page 654 of 1036
REJ09B0254-0600
request, then underflow error ocurs and transmit operation stops.
may fail, depending on the timing relationship between transmit FIFO write in and read out.
receive may fail, due to unexpected overflow errors caused on the manner that only one data
transfer request exceeding watermark of receive FIFO.
receive FIFO.
receive may fail, depending on the timing relationship between receive FIFO write in and read
out. In this case, the statuses of full, underflow, and overflow may not be reflected to flags.
With referring to transmit FIFO transfer request interrupt (SIFTXI) caused by under watermark
of transmit FIFO, write the exactly same number of data with that of transmit FIFO empty
slots with DMA auto request.
At that time, make sure to set the watermark value so as not to occur transmit FIFO empty nor
underflow when transmit operation.
Example: When 12 empty slots are set to transmit FIFO, write 12 data to transmit FIFO with
With referring to receive FIFO transfer request interrupt (SIFRXI) caused by over watermark
of receive FIFO, read the (valid number – 2) of data from receive FIFO with DMA auto
request.
Read operation shall be done before next receive data write.
(b) Transmit two 8-bit units of data at once. Then, after the 16-bit data is received by the
Notes on Using the SIOF with Versions Previous to the SH7727B
SH7727, separate the upper and lower 8-bit portions and treat them as two 8-bit units of
data. They can then be used as 8-bit slot length LSB-first data.
DMA auto request by transmit FIFO transfer interrupt (SIFTXI).