HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 400

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Bus State Controller (BSC)
Refreshing: The bus state controller is provided with a function for controlling synchronous
DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting
the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retain is low, can be activated by setting both the
RMODE bit and the RFSH bit to 1.
1. Auto-Refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0
in RTCSR, and the value set in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be
set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the
settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2 to
CKS0 setting. When the clock is selected by CKS2 to CKS0, RTCNT starts counting up from the
value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the
two values are the same, a refresh request is generated and an auto-refresh is performed. At the
same time, RTCNT is cleared to zero and the count-up is restarted. Figure 12.18 shows the auto-
refresh cycle timing.
All-bank precharging is performed in the Tp cycle, then an REF command is issued in the TRr
cycle following the interval specified by the TPC bits in MCR. After the TRr cycle, new command
output cannot be performed for the duration of the number of cycles specified by the TRAS bits in
MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS and TPC bits must
be set so as to satisfy the synchronous DRAM refresh cycle time stipulation (active/active
command delay time).
Auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset.
Rev.6.00 Mar. 27, 2009 Page 342 of 1036
REJ09B0254-0600
H'00000000
RTCSR.CKS(2−0)
RTCNT
CMF
External bus
RTCOR value
CMF flag cleared by start of
refresh cycle
Figure 12.18 Auto-Refresh Operation
= 000
≠ 000
RTCNT cleared to 0 when
RTCNT = RTCOR
Auto-refresh cycle
Time