DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 404
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2552BR26DV
Manufacturer:
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Quantity:
10 000
- Current page: 404 of 980
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Section 11 8-Bit Timers (TMR)
Channel 2
• Timer counter_2 (TCNT_2)
• Time constant register A_2 (TCORA_2)
• Time constant register B_2 (TCORB_2)
• Timer control register_2 (TCR_2)
• Timer control/status register_2 (TCSR_2)
Channel 3
• Timer counter_3 (TCNT_3)
• Time constant register A_3 (TCORA_3)
• Time constant register B_3 (TCORB_3)
• Timer control register_3 (TCR_3)
• Timer control/status register_3 (TCSR_3)
11.3.1
Each TCNT is an 8-bit up-counter. TCNT_0 and TCNT_1 (or TCNT_2 and TCNT_3) comprise a
single 16-bit register, so they can be accessed together by word access.
This clock source is selected by the clock select bits, CKS2 to CKS0, in TCR. TCNT can be
cleared by an external reset input signal or compare-match signals A and B. The CCLR1 and
CCLR0 bits in TCR select the method of TCNT clearing.
When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1. The
initial value of TCNT is H'00.
11.3.2
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_2 and
TCORA_3) comprise a single 16-bit register, so they can be accessed together by word access.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is
disabled during the T
The timer output from the TMO pin can be freely controlled by the compare-match signal A and
the settings of the output select bits, OS1 and OS0, in TCSR.
The initial value of TCORA is H'FF.
Rev. 6.00 Sep. 24, 2009 Page 356 of 928
REJ09B0099-0600
Timer Counter (TCNT)
Time Constant Register A (TCORA)
2
state of a TCORA write cycle.
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