DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 849

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.4
22.4.1
A transition is made to software standby mode when the SLEEP instruction is executed while the
SSBY bit in SBYCR = 1 and the LSON bit in LPWRCR = 0, and the PSS bit in TCSR_1
(WDT_1) = 0. In this mode, the CPU, on-chip peripheral modules, and oscillator all stop.
However, the contents of the CPU's internal registers and the states of on-chip peripheral modules
other than the on-chip RAM data, HCAN*
the states of I/O ports are retained. In this mode the oscillator stops, and therefore power
consumption is significantly reduced.
Notes: 1. Supported only by the H8S/2556 Group.
22.4.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7), or by
means of the RES pin, MRES pin, or STBY pin.
• Clearing with an interrupt
• Clearing with the RES pin or MRES pin
• Clearing with the STBY pin
When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to
the entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit/pin function switching bit to 1 and ensure that no interrupt with a higher priority
than interrupts IRQ0 to IRQ7 is generated. Software standby mode cannot be cleared if the
interrupt has been masked on the CPU side or has been designated as a DTC activation source.
When the RES pin or MRES pin is driven low, clock oscillation is started. At the same time as
clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin and MRES
pin must be held low until clock oscillation settles. When the RES pin or MRES pin goes high,
the CPU begins reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
2. Supported only by the H8S/2552 Group.
Software Standby Mode
Transition to Software Standby Mode
Clearing Software Standby Mode
1
, IEB*
2
A/D converter, and some IIC2 functions, and
Rev. 6.00 Sep. 24, 2009 Page 801 of 928
Section 22 Power-Down Modes
REJ09B0099-0600