SAF-C161PI-L25F CA Infineon Technologies, SAF-C161PI-L25F CA Datasheet - Page 49

• Manufacturer Part Number: SAF-C161PI-L25F CA
• Description: IC MCU 16BIT ROM/LESS TQFP-100-1
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161PI-L25F CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 3 KB
• Interface Type: 1xASC, 1xSSC, 1xl2C
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: F161PIL25FCAXT; SAF-C161PI-L25FCA; SAF-C161PI-L25FCAINTR; SAF-C161PI-L25FCATR; SAF-C161PI-L25FCATR; SAFC161PIL25FCAXT; SP000014363

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and figure below).
For a period of N * TCL the minimum value is computed using the corresponding
deviation D
where N = number of consecutive TCLs
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below).
Figure 12
Data Sheet
26.5
20
10
1
( N * TCL)
1
Max.jitter D [ns]
This approximated formula is valid for
1
N
min
:
5
Approximated Maximum Accumulated PLL Jitter
= 3TCL
min
40 and 10MHz
= N * TCL
10
NOM
- 1.288 ns = 58.7 ns (@
NOM
f
CPU
- D
20
N
25MHz.
47
and 1
D
N
[ns] = (13.3 + N *6.3) /
3
N
CPU
= (13.3 + 3 * 6.3) / 25 = 1.288 ns,
40.
= 25 MHz).
40
CPU
[MHz],
10 MHz
16 MHz
20 MHz
25 MHz
&3,
1999-07
N