SAK-C167CS-L33M CA+ Infineon Technologies, SAK-C167CS-L33M CA+ Datasheet - Page 62

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SAK-C167CS-L33M CA+

Manufacturer Part Number
SAK-C167CS-L33M CA+
Description
IC MCU 16BIT 33MHZ MQFP-144
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAK-C167CS-L33M CA+

Core Processor
C166
Core Size
16-Bit
Speed
33MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Type
ROMless
Ram Size
11K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144- BSQFP
Data Bus Width
16 bit
Data Ram Size
11 KB
Interface Type
ASC, CAN, SSC
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Packages
PG-MQFP-144
Max Clock Frequency
33.0 MHz
Sram (incl. Cache)
11.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
24
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
K167CSL33MCAZNT
K167CSL33MCAZXT
SAKC167CSL33MCAT
SP000017988
SP000103489
Direct Drive
When direct drive is configured (CLKCFG = 011
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of
f
f
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
For two consecutive TCLs the deviation caused by the duty cycle of
so the duration of 2TCL is always 1/
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/
Data Sheet
CPU
OSC
.
TCL
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
min
= 1/
f
OSC
f
CPU
× DC
directly follows the frequency of
min
(DC = duty cycle)
f
OSC
. The minimum value TCL
58
B
) the on-chip phase locked loop is
f
OSC
so the high and low time of
f
OSC
min
therefore has to
is compensated
C167CS-4R
f
V2.2, 2001-08
OSC
C167CS-L
.

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