SAK-C167CS-L40M Infineon Technologies AG, SAK-C167CS-L40M Datasheet

no-image

SAK-C167CS-L40M

Manufacturer Part Number
SAK-C167CS-L40M
Description
16 Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheet
Da ta She et, V2. 2, Aug . 2 00 1
C 1 6 7 C S - 4 R
C 1 6 7 C S - L
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l e r
M i c r o c o n t r o l l e r s
N e v e r
s t o p
t h i n k i n g .

Related parts for SAK-C167CS-L40M

SAK-C167CS-L40M Summary of contents

Page 1

...

Page 2

... Edition 2001-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...

Page 3

...

Page 4

C167CS Revision History: Previous Version: Page Subjects (major changes from V2.1, 2000-12 to V2.2, 2001-08) 4 Figure 2 corrected (pins 98, 99) 25, 27 Figure 5 and 50ff Output voltage/current specification improved 52f Limit values for oscillator 54 Figure 10 ...

Page 5

Single-Chip Microcontroller C166 Family C167CS-4R, C167CS-L • High Performance 16-bit CPU with 4-Stage Pipeline – 80/60/50 ns Instruction Cycle Time at 25/33/40 MHz CPU Clock – 400/303/250 ns Multiplication (16 × 16 bit), 800/606/500 ns Division (32-/16-bit) – Enhanced ...

Page 6

... As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 C167CS Derivative Synopsis 1) Derivative SAK-C167CS-LM SAB-C167CS-LM SAK-C167CS-L33M SAB-C167CS-L33M SAK-C167CS-L40M SAB-C167CS-L40M SAK-C167CS-4RM SAB-C167CS-4RM SAK-C167CS-4R33M SAB-C167CS-4R33M SAK-C167CS-4R40M SAB-C167CS-4R40M 1) This Data Sheet is valid for devices starting with and including design step BA. ...

Page 7

Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the ...

Page 8

Pin Configuration (top view) P6.0/CS0 1 2 P6.1/CS1 P6.2/CS2 3 P6.3/CS3 4 P6.4/CS4 5 P6.5/HOLD 6 P6.6/HLDA 7 P6.7/BREQ 8 *P8.0/CC16IO 9 *P8.1/CC17IO 10 *P8.2/CC18IO 11 *P8.3/CC19IO 12 P8.4/CC20IO 13 P8.5/CC21IO 14 P8.6/CC22IO 15 P8.7/CC23IO ...

Page 9

Table 2 Pin Definitions and Functions Symbol Pin Input Num. Outp P6.6 7 I/O P6 P8.0 ...

Page 10

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P7.4 23 I/O P7.5 24 I/O P7.6 25 I/O P7 ...

Page 11

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P2.0 47 I/O P2.1 48 I/O P2.2 49 I/O P2.3 50 I/O P2.4 51 I/O P2.5 52 I/O P2.6 53 I/O P2.7 54 I/O P2.8 57 ...

Page 12

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P3.8 75 ...

Page 13

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P4.7 ...

Page 14

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. ALE PORT0 IO P0L.0-7 100- 107 P0H.0-7 108, 111- 117 Data Sheet Function Address Latch Enable Output. Can be used for latching the ...

Page 15

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. PORT1 IO P1L.0-7 118- 125 P1H.0-7 128- 135 P1L.0 118 I P1L.1 119 I P1L.2 120 I P1L.3 121 I P1L.4 122 I P1L.5 123 I P1L.6 124 ...

Page 16

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. RSTIN 140 I/O RST 141 O OUT NMI 142 – AREF V 38 – AGND Data Sheet Function Reset Input with Schmitt-Trigger characteristics. A low ...

Page 17

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. V 17, 46, – DD 56, 72, 82, 93, 109, 126, 136, 144 V 18, 45, – SS 55, 71, 83, 94, 110, 127, 139, 143 1) The ...

Page 18

Functional Description The architecture of the C167CS combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. ...

Page 19

Memory Organization The memory space of the C167CS is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire ...

Page 20

External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...

Page 21

Note: When one or both of the on-chip CAN Modules are used with the interface lines assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to ...

Page 22

The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...

Page 23

Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C167CS is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...

Page 24

Table 3 C167CS Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...

Page 25

Table 3 C167CS Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...

Page 26

The C167CS also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...

Page 27

Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse ...

Page 28

Table 5 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible. Mode 1 Pin toggles on each compare match; several compare events per timer period are possible. Mode 2 Interrupt-only ...

Page 29

CPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 16 Capture Inputs 16 Compare Outputs CCxIO CPU GPT2 Timer T6 Over/Underflow ...

Page 30

General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...

Page 31

T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of ...

Page 32

This allows the C167CS to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN ...

Page 33

Real Time Clock The Real Time Clock (RTC) module of the C167CS consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). ...

Page 34

A/D Converter For analog signal measurement, a 10-bit A/D converter with 24 multiplexed input channels (16 standard channels and 8 extension channels) and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The ...

Page 35

Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...

Page 36

CAN-Modules The integrated CAN-Modules handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as ...

Page 37

Parallel Ports The C167CS provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction ...

Page 38

Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on ...

Page 39

Power Management The C167CS provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the C167CS into ...

Page 40

Instruction Set Summary Table 6 lists the instructions of the C167CS in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the ...

Page 41

Table 6 Instruction Set Summary (cont’d) Mnemonic Description MOV(B) Move word (byte) data MOVBS Move byte operand to word operand with sign extension MOVBZ Move byte operand to word operand with zero extension JMPA, JMPI, Jump absolute/indirect/relative if condition is ...

Page 42

Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C167CS in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter ...

Page 43

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address C1UAR EFn2 X --- H C1UGML EF08 X --- H C1UMLM EF0C X --- H C2BTR EE04 X --- H C2CSR EE00 X --- H C2GMS EE06 X --- ...

Page 44

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address CC17 FE62 H CC17IC b F162 CC18 FE64 H CC18IC b F164 CC19 FE66 H CC19IC b F166 CC1IC b ...

Page 45

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address CC30 FE7C H CC30IC b F18C CC31 FE7E H CC31IC b F194 CC3IC b FF7E H CC4 FE88 H CC4IC b FF80 H ...

Page 46

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address DP1L b F104 DP1H b F106 DP2 b FFC2 H DP3 b FFC6 H DP4 b FFCA H DP6 b FFCE H DP7 ...

Page 47

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address ONES b FF1E H P0H b FF02 H P0L b FF00 H P1DIDIS FEA4 H P1H b FF06 H P1L b FF04 FFC0 ...

Page 48

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address POCON4 F08C POCON6 F08E POCON7 F090 POCON8 F092 PP0 F038 PP1 F03A E 1D ...

Page 49

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C S0TBUF FEB0 H S0TIC b FF6C H SP FE12 H SSCBR F0B4 SSCCON ...

Page 50

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address T14 F0D2 T14REL F0D0 FE40 H T2CON b FF40 H T2IC b FF60 H T3 FE42 H T3CON b FF42 H T3IC ...

Page 51

Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address XP3IC b F19E XPERCON F024 ZEROS b FF1C H 1) The system configuration is selected during reset. 2) The reset value depends on ...

Page 52

Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with V respect to ground ( ) SS Input ...

Page 53

... DD V > 0 < C167CS-4R C167CS-L Unit Notes V Active mode MHz CPUmax V PowerDown mode V Reference voltage 2)3) mA Per pin Pin drivers in fast edge mode ° C SAB-C167CS … ° C SAF-C167CS … ° C SAK-C167CS … - 0.5 V). The absolute sum of input overload V2.2, 2001-08 4) ...

Page 54

Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CS and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...

Page 55

DC Characteristics (cont’d) (Operating Conditions apply) Parameter Input leakage current (all other) 6) RSTIN inactive current 6) RSTIN active current READY/RD/WR inact. current READY/RD/WR active current 9) ALE inactive current 9) ALE active current 9) Port 6 inactive current 9) ...

Page 56

Table 10 Current Limits for Port Output Drivers Port Output Driver Maximum Output Current I ( P2 (PORT0, PORT1, ----- Port 4, ALE, RD, WR, BHE, CLKOUT, 2) RSTOUT, RSTIN ) All other outputs ----- 1) ...

Page 57

A] I 3000 2000 1000 10 Figure 9 Idle and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet C167CS-4R C167CS-L I IDOmax I IDOtyp I PDRmax I PDOmax 40 f [MHz] ...

Page 58

I [mA] 140 120 100 Figure 10 Supply/Idle Current as a Function of Operating Frequency Data Sheet C167CS-4R C167CS-L I DD5max I DD5typ I IDX5max I IDX5typ 40 f [MHz] CPU V2.2, ...

Page 59

AC Characteristics Definition of Internal Timing The internal operation of the C167CS is controlled by the internal CPU clock edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external ...

Page 60

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Table 11 C167CS Clock Generation Modes CLKCFG CPU ...

Page 61

Due to this adaptation to the input clock the frequency locked to . The slight variation causes a jitter of OSC duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs ...

Page 62

Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the ...

Page 63

AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 12 External Clock Drive Characteristics Parameter Symbol t Oscillator period SR 25 OSC 2) t High time Low time Rise ...

Page 64

A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source ...

Page 65

As the default basic clock after reset is a valid factor as early as possible. A timeframe of approx. 6000 CPU clock cycles is sufficient to ensure a proper reset calibration. This corresponds to minimum 300 instructions (worst case: ...

Page 66

Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at Figure 14 Input Output Waveforms V + 0.1 V ...

Page 67

AC Characteristics Table 15 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to For a ...

Page 68

Table 17 External Bus Cycle Timing (Operating Conditions apply) Parameter Output delay from CLKOUT falling edge Valid for: address (MUX on PORT0), write data out Output delay from CLKOUT edge Valid for: latched CS, ALE (normal) Output delay from CLKOUT ...

Page 69

The bandwidth of a parameter (minimum and maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies ...

Page 70

CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A0, BHE WRL, WRH, WR, WrCS D15-D0 Note: Write data is deactivated 1 TCL earlier if early write is enabled (same timing). Figure 17 Demultiplexed Bus, Write ...

Page 71

CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A0, BHE RD, RdCS D15-D0 Figure 18 Demultiplexed Bus, Read Access Data Sheet Normal ALE Cycle Extended ALE Cycle ...

Page 72

CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A16, BHE WRL, WRH, WR, WrCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Note: Write data is deactivated 2 TCL earlier if early write ...

Page 73

CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A16, BHE RD, RdCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Figure 20 Multiplexed Bus, Read Access Data Sheet Normal ALE Cycle tc 11 ...

Page 74

Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be ...

Page 75

Running Cycle CLKOUT D15-D0 D15-D0 Command (RD, WR) Synchronous READY tc 25 Asynchronous 4) 3) READY Figure 21 READY Timing Data Sheet ...

Page 76

External Bus Arbitration Table 20 Bus Arbitration Timing (Operating Conditions apply) Parameter HOLD input setup time to CLKOUT falling edge CLKOUT to BREQ delay CLKOUT to HLDA delay 1) CSx release CSx drive 1) Other signals release 1) Other signals ...

Page 77

CLKOUT tc 28 HOLD HLDA BREQ CS Other Signals Figure 22 External Bus Arbitration, Releasing the Bus Notes 1) The C167CS will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ ...

Page 78

CLKOUT HOLD HLDA BREQ CS Other Signals Figure 23 External Bus Arbitration, (Regaining the Bus) Notes 4) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by ...

Page 79

External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CS can be accessed (during hold states external master like an asynchronous SRAM. Table 21 XRAM Access Timing (Operating Conditions apply) Parameter Address setup time ...

Page 80

Package Outlines P-MQFP-144-6 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 76 C167CS-4R C167CS-L Dimensions in mm V2.2, 2001-08 ...

Page 81

... Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher Published by Infineon Technologies AG ...

Related keywords