PIC16LC774/PQ Microchip Technology, PIC16LC774/PQ Datasheet - Page 139

• Manufacturer Part Number: PIC16LC774/PQ
• Description: IC MCU OTP 4KX14 A/D PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.12
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
FIGURE 12-12: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 12-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
1999 Microchip Technology Inc.
Watchdog Timer (WDT)
Name
Config. bits
OPTION_REG
Figure 12-1
WDT Timer
Enable Bit
WDT
for the full description of the configuration word bits.
RBPU
Bit 7
From TMR0 Clock Source
(Figure
(1)
4-2)
BODEN
INTEDG
Bit 6
Advance Information
0
1
(1)
PSA
M
U
X
T0CS
Bit 5
CP1
T0SE
The WDT can be permanently disabled by clearing
configuration bit WDTE
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler may be assigned using the
OPTION_REG register.
.
Bit 4
CP0
0
Note:
Note:
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
PWRTE
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
1
Bit 3
PSA
8
(1)
PSA
To TMR0
(Section
WDTE
Bit 2
PS2
PIC16C77X
PS2:PS0
(Section
12.1).
FOSC1
DS30275A-page 139
Bit 1
PS1
4-2)
FOSC0
Bit 0
PS0