PIC16LC774/PQ Microchip Technology, PIC16LC774/PQ Datasheet - Page 62

• Manufacturer Part Number: PIC16LC774/PQ
• Description: IC MCU OTP 4KX14 A/D PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16C77X
8.1.7
In master mode all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in sleep mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP interrupt
flag bit will be set and if enabled will wake the device
from sleep.
TABLE 8-1
DS30275A-page 62
Legend:
Note 1:
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
13h
14h
94h
Address
SLEEP OPERATION
x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the SSP in SPI mode.
These bits are reserved on the 28-pin devices, always maintain these bits clear.
INTCON
PIR1
PIE1
SSPBUF
SSPCON
SSPSTAT
Name
REGISTERS ASSOCIATED WITH SPI OPERATION
Synchronous Serial Port Receive Buffer/Transmit Register
PSPIE
PSPIF
WCOL
Bit 7
SMP
GIE
(1)
(1)
SSPOV
ADIE
Bit 6
PEIE
ADIF
CKE
SSPEN
Advance Information
RCIE
Bit 5
RCIF
T0IE
D/A
INTE
Bit 4
TXIF
TXIE
CKP
P
SSPM3
SSPIE
SSPIF
RBIE
Bit 3
S
8.1.8
A reset disables the MSSP module and terminates the
current transfer.
CCP1IF
CCP1IE
SSPM2
Bit 2
T0IF
R/W
EFFECTS OF A RESET
TMR2IE
TMR2IF
SSPM1
INTF
Bit 1
UA
TMR1IF
TMR1IE
SSPM0
RBIF
Bit 0
BF
1999 Microchip Technology Inc.
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
POR, BOR
MCLR, WDT
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000