ATMEGA163L-4AI Atmel, ATMEGA163L-4AI Datasheet - Page 12

• Manufacturer Part Number: ATMEGA163L-4AI
• Description: IC AVR MCU 16K A/D 2.7V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Program and Data
Addressing Modes
Register Direct, Single
Register Rd
12
ATmega163(L)
The lower 1,120 Data Memory locations address the Register File, the I/O Memory, and
the internal data SRAM. The first 96 locations address the Register File + I/O Memory,
and the next 1,024 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Dis-
placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect Addressing Pointer
Registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features a 63 address locations reach from the
base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 1,024 bytes of
internal data SRAM in the ATmega163 are all accessible through all these addressing
modes.
The ATmega163 AVR Enhanced RISC microcontroller supports powerful and efficient
addressing modes for access to the Program Memory (Flash) and Data Memory
(SRAM, Register File, and I/O Memory). This section describes the different addressing
modes supported by the AVR architecture. In the figures, OP means the operation code
part of the instruction word. To simplify, not all figures show the exact location of the
addressing bits.
Figure 10. Direct Single Register Addressing
The operand is contained in register d (Rd).
1142E–AVR–02/03