ATMEGA163L-4AI Atmel, ATMEGA163L-4AI Datasheet - Page 69

• Manufacturer Part Number: ATMEGA163L-4AI
• Description: IC AVR MCU 16K A/D 2.7V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The SPI Data Register – SPDR
1142E–AVR–02/03
• Bit 6 – WCOL : Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one), and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega163 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is set (one) the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 26). This means that the minimum SCK period will be two
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to
work at f
The SPI interface on the ATmega163 is also used for Program memory and EEPROM
downloading or uploading. See page 155 for Serial Programming and verification.
The SPI Data Register is a read/write register used for data transfer between the Regis-
ter File and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Bit
$0F ($2F)
Read/Write
Initial Value
ck
/4 or lower.
MSB
R/W
X
7
R/W
X
6
R/W
5
X
R/W
4
X
R/W
X
3
R/W
X
2
ATmega163(L)
R/W
X
1
LSB
R/W
0
X
Undefined
SPDR
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