ATMEGA8-16AC Atmel, ATMEGA8-16AC Datasheet - Page 100

• Manufacturer Part Number: ATMEGA8-16AC
• Description: IC AVR MCU 8K 16MHZ COM 32-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8-16AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA816AC

Input Capture Register
1 – ICR1H and ICR1L
Timer/Counter
Interrupt Mask
Register – TIMSK
100
ATmega8(L)
(1)
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare Interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes
are written simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the
other 16-bit registers.
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Cap-
ture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt
Vector (see
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(see
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
“Interrupts” on page
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
See “Accessing 16-bit Registers” on page 77.
described in this section. The remaining bits are described in their respective timer sections
“Interrupts” on page
OCIE2
R/W
R/W
7
0
7
0
See “Accessing 16-bit Registers” on page 77.
“Interrupts” on page
“Interrupts” on page
TOIE2
R/W
R/W
6
0
6
0
46) is executed when the TOV1 Flag, located in TIFR, is set.
TICIE1
R/W
R/W
5
0
5
0
46) is executed when the ICF1 Flag, located in TIFR, is set.
OCIE1A
R/W
R/W
0
0
4
4
ICR1[15:8]
ICR1[7:0]
46) is executed when the OCF1A Flag, located in
46) is executed when the OCF1B Flag, located in
OCIE1B
R/W
R/W
3
0
3
0
TOIE1
R/W
R/W
2
0
2
0
R/W
R
1
0
1
–
0
TOIE0
R/W
R/W
0
0
0
0
ICR1H
ICR1L
TIMSK
2486Z–AVR–02/11