ATMEGA8-16AC Atmel, ATMEGA8-16AC Datasheet - Page 126

IC AVR MCU 8K 16MHZ COM 32-TQFP

ATMEGA8-16AC

Manufacturer Part Number
ATMEGA8-16AC
Description
IC AVR MCU 8K 16MHZ COM 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8-16AC

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA816AC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8-16AC
Manufacturer:
Atmel
Quantity:
10 000
SPI Status Register –
SPSR
126
ATmega8(L)
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
CPOL functionality is summarized below:
Table 48. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
example. The CPHA functionality is summarized below:
Table 49. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 50. Relationship Between SCK and the Oscillator Frequency
Bit
Read/Write
Initial Value
SPI2X
CPOL
CPHA
0
0
0
0
1
1
1
1
0
1
0
1
SPIF
R
7
0
Figure 59 on page 128
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
R
5
0
Sample
Falling
Rising
Setup
Figure 59 on page 128
SPR0
R
0
4
0
1
0
1
0
1
0
1
and
3
R
0
Figure 60 on page 128
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
0
and
Trailing Edge
Trailing Edge
R
1
0
Figure 60 on page 128
Sample
Falling
Rising
Setup
SPI2X
R/W
0
0
for an example. The
SPSR
2486Z–AVR–02/11
for an
osc
is

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