PIC16C770-E/SO Microchip Technology, PIC16C770-E/SO Datasheet - Page 99

• Manufacturer Part Number: PIC16C770-E/SO
• Description: IC MCU OTP 2KX14 A/D PWM 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: AC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC16C770E/SO

9.2.17.2
During a Repeated START condition, a bus collision
occurs if:
a)
b)
When the master module de-asserts SDA and the pin
is allowed to float high, the BRG is loaded with
SSPADD<6:0>, and counts down to ‘0’. The SCL pin is
then de-asserted, and when sampled high, the SDA pin
is sampled. If SDA is low, a bus collision has occurred
(i.e., another master is attempting to transmit a data
FIGURE 9-27:
FIGURE 9-28:
2002 Microchip Technology Inc.
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
BUS COLLISION DURING A REPEATED
START CONDITION
’0’
’0’
’0’
’0’
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
Advance Information
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
’0’). If however SDA is sampled high, then the BRG is
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs,
because no two masters can assert SDA at exactly the
same time.
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
START condition.
If at the end of the BRG time-out both SCL and SDA are
still high, the SDA pin is driven low, the BRG is
reloaded, and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is com-
plete (Figure 9-27).
PIC16C717/770/771
T
Cleared in software
BRG
Interrupt cleared
in software
’0’
’0’
DS41120B-page 97
’0’
’0’