PIC16C770-I/P Microchip Technology, PIC16C770-I/P Datasheet
PIC16C770-I/P
Specifications of PIC16C770-I/P
Related parts for PIC16C770-I/P
PIC16C770-I/P Summary of contents
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... CMOS Microcontrollers 2002 Microchip Technology Inc. M PIC16C717/770/771 Data Sheet with 10/12-bit A/D DS41120B ...
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... Serialized Quick Term Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... PWM max. resolution is 10-bit - Enhanced PWM: - Single, Half-Bridge and Full-Bridge Output modes - Digitally programmable deadband delay • Analog-to-Digital converter: - PIC16C770/771 12-bit resolution - PIC16C717 10-bit resolution • On-chip absolute bandgap voltage reference generator • Programmable Brown-out Reset (PBOR) circuitry • Programmable Low-Voltage Detection (PLVD) circuitry • ...
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... PP RA6/OSC2/CLKOUT ( ( RB7/T1OSI/P1D RA2/AN2/V -/VRL REF RB6/T1OSO/T1CKI/P1C RA3/AN3/V +/VRH REF RB5/SDO/P1B RB0/AN4/INT RB4/SDI/SDA RB1/AN5/SS PIC16C717 PIC16C770 MHz MHz POR, BOR, MCLR, POR, BOR, MCLR, WDT (PWRT, OST) WDT (PWRT, OST 256 256 10 10 Ports A,B Ports A MSSP MSSP – 6 input channels 6 input channels – ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2002 Microchip Technology Inc. PIC16C717/770/771 DS41120B-page 3 ...
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... PIC16C717/770/771 NOTES: DS41120B-page 4 2002 Microchip Technology Inc. ...
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... TM There are three devices (PIC16C717, PIC16C770 and Manual, PIC16C771) covered by this data sheet. The PIC16C717 device comes in 18/20-pin packages and the PIC16C770/771 devices come in 20-pin packages. ...
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... SS Watchdog Brown-out AV DD 12-bit ADC AV SS Timer0 Enhanced CCP (ECCP) Note 1: Higher order bits are from the STATUS register. 2: Program memory for PIC16C770 14. Program memory for PIC16C771 14. DS41120B-page 6 8 Data Bus RAM File (13-bit) Registers 256 x 8 RAM (1) Addr 9 Addr MUX ...
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... RB2/SCK/SCL SCK SCL RB3 RB3/CCP1/P1A CCP1 P1A RB4 RB4/SDI/SDA SDI SDA RB5 RB5/SDO/P1B SDO P1B Note 1: Bit programmable pull-ups. 2: Only in PIC16C770/771 devices. 2002 Microchip Technology Inc. PIC16C717/770/771 Input Output Type Type ST CMOS Bi-directional I/O AN A/D input ST CMOS Bi-directional I/O AN A/D input ...
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... P1C RB7 RB7/T1OSI/P1D T1OSI P1D ( ( Note 1: Bit programmable pull-ups. 2: Only in PIC16C770/771 devices. DS41120B-page 8 Input Output Type Type (1) TTL CMOS Bi-directional I/O XTAL Crystal/Resonator CMOS TMR1 clock input CMOS PWM P1C output (1) TTL CMOS Bi-directional I/O XTAL TMR1 crystal/resonator CMOS PWM P1D output ...
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... The PIC16C717/770/771 devices have a 13-bit pro- gram counter capable of addressing pro- gram memory space. The PIC16C717 and the PIC16C770 have words of program memory. The PIC16C771 has words of program mem- ory. Accessing a location above the physically imple- mented address will cause a wrap-around. ...
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... Bank 3 2002 Microchip Technology Inc. ...
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... Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 2002 Microchip Technology Inc. PIC16C717/770/771 The special function registers can be classified into two sets ...
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... 0000 0000 34 1111 1111 34 1111 0000 62 0000 0000 — — — — — — — — 102 0000 ---- LVV1 LVV0 101 --00 0101 25 --11 1111 107 xxxx xxxx — — 107 0000 ---- 2002 Microchip Technology Inc. ...
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... Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 2002 Microchip Technology Inc. PIC16C717/770/771 Bit 5 Bit 4 ...
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... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown 2002 Microchip Technology Inc. ...
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... Note 1: Individual weak pull- pins can be enabled/disabled from the weak pull-up PORTB Register (WPUB). Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 ...
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... R/W-0 R/W-0 R/W-0 R/W-0 T0IE INTE RBIE T0IF (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-x INTF RBIF bit Bit is unknown 2002 Microchip Technology Inc. ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 U-0 R/W-0 ADIE — ...
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... U-0 U-0 R/W-0 R/W-0 — — SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2002 Microchip Technology Inc. ...
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... Unimplemented: Read as '0' bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Bus Collision interrupt is enabled 0 = Bus Collision interrupt is disabled bit 2-0 Unimplemented: Read as '0' Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 U-0 U-0 U-0 R/W-0 — — — BCLIE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... U-0 U-0 U-0 R/W-0 — — — BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 U-0 U-0 — — — bit Master was x = Bit is unknown 2002 Microchip Technology Inc. ...
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... BOR: Brown-out Reset Status bit (See Section 2.2.2.8 Note Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don’ ...
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... The tenth push overwrites the second push (and so on). FIGURE 2-4: LOADING DIFFERENT SITUATIONS PCH PCL PCLATH<4:0> 8 ALU 5 PCLATH PCH PCL 12 1110 PCLATH<4:3> Opcode <10:0> 2 PCLATH 2002 Microchip Technology Inc. Instruction with PCL as Destination 0 GOTO, CALL ...
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... Direct Addressing RP1:RP0 6 from opcode bank select location select 00h Data Memory(1) 7Fh Bank 0 Note 1: For register file map detail see Figure 2-3. 2002 Microchip Technology Inc. PIC16C717/770/771 EXAMPLE 2-1: movlw movwf NEXT clrf incf btfss goto CONTINUE : An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS< ...
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... PIC16C717/770/771 NOTES: DS41120B-page 24 2002 Microchip Technology Inc. ...
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... V inputs, and the onboard bandgap reference out- REF puts. When the analog peripherals are using any of 2002 Microchip Technology Inc. PIC16C717/770/771 present on a pin, the pin must be configured as an ana- log input to prevent unnecessary current draw from the power supply. The Analog Select Register (ANSEL) allows the user to individually select the Digital/Analog mode on these pins ...
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... STATUS, RP0 ; Return to Bank 0 FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0, RA1/AN1/LVDIN Data Latch Data Bus D WR PORT CK TRIS Mode D WR TRIS CK RD TRIS Analog Select D WR ANSEL CK RD PORT To A/D Converter input or LVD Module input DS41120B-page Schmitt Q Trigger 2002 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RA2/AN2/V Data Bus WR PORT TRIS Mode WR TRIS RD TRIS Analog Select WR ANSEL RD PORT To A/D Converter input and inputs REF REF (From V VRH, VRL output enable 2002 Microchip Technology Inc. PIC16C717/770/771 -/VRL AND RA3/AN3/V REF Data Latch VRH, VRL outputs -LVD-BOR Module) REF ...
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... PIC16C717/770/771 FIGURE 3-3: BLOCK DIAGRAM OF RA4/T0CKI Data Latch Data Bus D WR Port CK TRIS Latch D WR TRIS CK RD TRIS RD PORT TMR0 clock input DS41120B-page Schmitt Trigger Input Buffer 2002 Microchip Technology Inc. ...
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... FIGURE 3-4: BLOCK DIAGRAM OF RA5/MCLR/V To MCLR Circuit Program Mode Data Bus RD TRIS RD PORT 2002 Microchip Technology Inc. PIC16C717/770/771 PP MCLR Filter HV Detect V SS Schmitt Trigger DS41120B-page 29 ...
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... FIGURE 3-5: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN (INTRC or ER) and CLKOUT CLKOUT (Fosc/ Data D Q Bus PORTA Data Latch TRISA TRIS Latch RD TRISA Q RD PORTA DS41120B-page 30 From OSC1 Oscillator Circuit [(ER or INTRC) and CLKOUT Schmitt Trigger Input Buffer 2002 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN Data D Q Bus PORTA Data Latch TRISA TRIS Latch INTRC RD TRISA Q RD PORTA 2002 Microchip Technology Inc. PIC16C717/770/771 To OSC2 Oscillator To Chip Clock Drivers Schmitt Trigger Vss D EN Circuit V DD Input Buffer EC Mode INTRC Schmitt Trigger Input Buffer ...
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... External clock input/ER resistor connection Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 ANS5 ANS4 ANS3 ANS2 ANS1 Description Value on: Value on all Bit 0 POR, other BOR RESETS xxxx 0000 uuuu 0000 RA0 1111 1111 1111 1111 ANS0 --11 1111 --11 1111 2002 Microchip Technology Inc. ...
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... The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. 2002 Microchip Technology Inc. PIC16C717/770/771 Each of the PORTB pins, if configured as input, also has an interrupt-on-change feature, which can be indi- vidually selected from the IOCB register ...
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... R/W-0 IOCB5 IOCB4 IOCB3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 WPUB2 WPUB1 WPUB0 bit Bit is unknown R/W-0 R/W-0 R/W-0 IOCB2 IOCB1 IOCB0 bit Bit is unknown 2002 Microchip Technology Inc. ...
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... Q RD PORT To INT input or MSSP module To A/D Converter 2002 Microchip Technology Inc. PIC16C717/770/771 The RB1 pin is multiplexed with the A/D converter ana- log input 5 and the MSSP module slave select input (RB1/AN5/SS). When the pin is used as analog input, the ANSEL register must have the proper value to select the RB1 pin as Analog mode ...
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... Spec. Func En. SDA, SDO, SCK, CCP1, P1A, P1B PORTB Reg PORT CK Q TRIS Reg TRIS TRIS IOCB Reg IOCB PORT SCK, SCL, CC, SDI, SDA inputs DS41120B-page 36 RBPU Set RBIF Q From RB<7:0> pins weak P pull- TTL Schmitt Trigger 2002 Microchip Technology Inc. ...
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... IOCB Reg IOCB CK Q TMR1 Clock Serial programming clock From RB7 Set RBIF From RB<7:0> pins Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB6 I/O port and P1C functions. 2002 Microchip Technology Inc. PIC16C717/770/771 Q RBPU CMOS Schmitt Trigger TMR1 Oscillator V ...
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... Serial programming input Schmitt Trigger Set RBIF Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB7 I/O port and P1D functions. DS41120B-page weak pull- RB6 Q T1OSCEN From Q D RB<7:0> pins EN TMR1 Oscillator TTL Input Buffer Q1 RD Port Q3 2002 Microchip Technology Inc. ...
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... OPTION_REG RBPU INTEDG 95h WPUB PORTB Weak Pull-up Control 96h IOCB PORTB Interrupt on Change Control 9Dh ANSEL — — Legend unknown unchanged. Shaded cells are not used by PORTB. 2002 Microchip Technology Inc. PIC16C717/770/771 Input Output Type Type (1) TTL CMOS Bi-directional I/O AN A/D input ...
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... PIC16C717/770/771 NOTES: DS41120B-page 40 2002 Microchip Technology Inc. ...
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... The PMDATH:PMDATL registers are loaded with the contents of program memory addressed by the PMADRH and PMADRL registers upon completion of a Program Memory Read command. 2002 Microchip Technology Inc. PIC16C717/770/771 When interfacing the program memory block, the PMDATH & PMDATL registers form a 2-byte word, which holds the 14-bit data. The PMADRH & ...
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... Bit is cleared R-x R-x R-x PMD10 PMD9 PMD8 bit Bit is unknown R-x R-x R-x PMD2 PMD1 PMD0 bit Bit is unknown R/W-x R/W-x R/W-x PMA10 PMA9 PMA8 bit Bit is unknown R/W-x R/W-x R/W-x PMA2 PMA1 PMA0 bit Bit is unknown 2002 Microchip Technology Inc. ...
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... BSF PMCON1,RD Executed here Executed here RD bit PMDATH PMDATL register 2002 Microchip Technology Inc. PIC16C717/770/771 the “ ” instruction to be ignored. The data BSF PMCON1,RD is available, in the very next cycle, in the PMDATH and PMDATL registers; therefore it can be read as 2 bytes in the following instructions. PMDATH and PMDATL ...
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... PMA11 PMA10 PMA9 PMA5 PMA4 PMA3 PMA2 PMA1 Value on: Value on all Bit 0 POR, other BOR RESETS 1--- ---0 1--- ---0 RD --xx xxxx --uu uuuu PMD8 xxxx xxxx uuuu uuuu PMD0 ---- xxxx ---- uuuu PMA8 xxxx xxxx uuuu uuuu PMA0 2002 Microchip Technology Inc. ...
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... T0SE T0CS Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram). 2002 Microchip Technology Inc. PIC16C717/770/771 Additional information on external clock requirements is available in the PICmicro™ Mid-Range MCU Family Reference Manual, (DS33023). ...
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... PS2 PS1 Data Bus 8 TMR0 reg Set flag bit T0IF on Overflow Value on: Value on all Bit 0 POR, other BOR RESETS xxxx xxxx uuuu uuuu RBIF 0000 000x 0000 000u 1111 1111 1111 1111 PS0 1111 1111 1111 1111 2002 Microchip Technology Inc. ...
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... Enables Timer1 0 = Stops Timer1 Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual, (DS33023). 6.1 ...
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... Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS41120B-page 48 TMR1 TMR1L TMR1ON T1SYNC on/off 1 Prescaler T1OSCEN Fosc/4 Enable Internal 0 Oscillator(1) Clock T1CKPS<1:0> TMR1CS Synchronized 0 clock input 1 Synchronize det 2 SLEEP input 2002 Microchip Technology Inc. ...
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... T1CON — — Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by the Timer1 module. 2002 Microchip Technology Inc. PIC16C717/770/771 6.3 Timer1 Interrupt The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1< ...
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... PIC16C717/770/771 NOTES: DS41120B-page 50 2002 Microchip Technology Inc. ...
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... T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 7.1 Timer2 Operation Timer2 can be used as the PWM time-base for PWM mode of the ECCP module. The TMR2 register is readable and writable, and is cleared on any device RESET ...
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... Prescaler TMR2 reg Fosc/4 1:1, 1:4, 1:16 2 Comparator EQ PR2 reg Value on: Value on Bit 0 POR, all other BOR RESETS 0000 000x 0000 000u RBIF -0-- 0000 -0-- 0000 TMR1IF -0-- 0000 -0-- 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 2002 Microchip Technology Inc. ...
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... PWM mode. P1A, P1C active low. P1B, P1D active low. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON and P1DEL reg- isters control the operation of ECCP ...
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... This is not the port data latch. 8.2.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro- nized Counter mode if the ECCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 2002 Microchip Technology Inc. CCPR1L TMR1L ...
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... CCP1CON PWM1M1 PWM1M0 DC1B1 Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1. 2002 Microchip Technology Inc. PIC16C717/770/771 FIGURE 8-2: Special event trigger will: RESET Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>). Special Event Trigger ...
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... The postscaler could be used to have a servo update rate at a different fre- quency than the PWM output. DS41120B-page 56 PWM1M1<1:0> CCP1M<3:0> CCP1/P1A TRISB<3> P1B TRISB<5> OUTPUT Q CONTROLLER P1C TRISB<6> P1D TRISB<7> P1DEL • OSC ) RB3/CCP1/P1A RB5/SDO/P1B RB6/T1OSO/T1CKI/ P1C RB7/T1OSI/P1D 2002 Microchip Technology Inc. ...
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... In the Single Output mode, the RB3/CCP1/P1A pin is used as the PWM output. Since the CCP1 output is multiplexed with the PORTB<3> data latch, the TRISB<3> bit must be cleared to make the CCP1 pin an output. 2002 Microchip Technology Inc. PIC16C717/770/771 FIGURE 8-4: SINGLE PWM OUTPUT Period ...
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... Output signals are shown as asserted high. DS41120B-page 58 The PWM output polarities must be selected before the PWM outputs are enabled. Charging the polarity con- figuration while the PWM outputs are active is not rec- ommended, since it may result in unpredictable operation. (1) 2002 Microchip Technology Inc. ...
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... FIGURE 8-7: EXAMPLE OF HALF-BRIDGE OUTPUT MODE APPLICATIONS PIC16C717/770/771 P1A P1B PIC16C717/770/771 P1A P1B 2002 Microchip Technology Inc. PIC16C717/770/771 V+ FET DRIVER FET DRIVER V- V+ FET DRIVER + - LOAD FET DRIVER LOAD + V - FET DRIVER FET DRIVER DS41120B-page 59 ...
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... Output signal is shown as asserted high. DS41120B-page 60 P1A, P1B, P1C and P1D outputs are multiplexed with PORTB<3> and PORTB<5:7> data latches. TRISB<3> and TRISB<5:7> bits must be cleared to make the P1A, P1B, P1C, and P1D pins output. Period (1) Period (1) 2002 Microchip Technology Inc. ...
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... FIGURE 8-9: EXAMPLE OF FULL-BRIDGE APPLICATION PIC16C717/770/771 P1D P1C P1A P1B 2002 Microchip Technology Inc. PIC16C717/770/771 V+ FET DRIVER + - LOAD FET DRIVER V- FET DRIVER FET DRIVER DS41120B-page 61 ...
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... P1D, will go to the inactive state. See Figure 8-10 for illustration. (1) PERIOD (2) , 4*Tosc or 16*T , depending on the Timer2 prescaler value, earlier when OSC OSC R/W-0 R/W-0 R/W-0 P1DEL2 P1DEL1 P1DEL0 bit 0 /4 (Tosc 4) OSC x = Bit is unknown PERIOD 2002 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC16C717/770/771 example, since the turn off time of the power devices is longer than the turn on time, a shoot-through current flows through the power devices, QB and QD, for the ...
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... TMR1IF -0-- 0000 -0-- 0000 TMR1IE -0-- 0000 -0-- 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu CCP1M0 0000 0000 0000 0000 0000 0000 0000 0000 2002 Microchip Technology Inc. ...
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... These peripheral devices may be serial EEPROMs, shift registers, dis- play drivers, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI™) 2 • Inter-Integrated Circuit (I C™) 2002 Microchip Technology Inc. PIC16C717/770/771 Advance Information DS41120B-page 65 ...
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... Value at POR DS41120B-page 66 R-0 R-0 R-0 CKE D mode only mode only mode only) 2 modes Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R-0 R-0 R-0 R bit Bit is unknown 2002 Microchip Technology Inc. ...
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... C Slave mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (used to ensure data setup time Master mode Unused in this mode Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... Slave mode with START and STOP condition interrupts Legend Readable bit - n = Value at POR DS41120B-page 68 /4 OSC /16 OSC /64 OSC / (4 (SSPADD+1) ) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information x = Bit is unknown 2002 Microchip Technology Inc. ...
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... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 R/W-0 R/W-0 R/W-0 ACKDT ACKEN ...
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... Advance Information MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Write SSPBUF reg SSPSR reg Shift bit0 Clock Enable Edge 2 Clock Select SSPM<3:0> 4 TMR2 Output 2 2 Edge Select Tosc Prescaler 4, 16, 64 Data to TX/RX in SSPSR Data direction bit 2002 Microchip Technology Inc. ...
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... SPI Master SSPM<3:0> = 00xxb Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb PROCESSOR 1 2002 Microchip Technology Inc. PIC16C717/770/771 9.1.2 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON reg- isters, and then set bit SSPEN ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit5 bit4 bit2 bit3 bit5 bit4 bit2 bit3 Advance Information ) Clock modes bit1 bit0 bit1 bit0 bit0 bit0 Next Q4 cycle after Q2 2002 Microchip Technology Inc. ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF 2002 Microchip Technology Inc. PIC16C717/770/771 SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desir- able, depending on the application ...
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... SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41120B-page 74 bit6 bit5 bit4 bit2 bit3 bit6 bit2 bit5 bit4 bit3 Advance Information bit1 bit0 bit0 Next Q4 cycle after Q2 bit1 bit0 bit0 Next Q4 cycle after Q2 2002 Microchip Technology Inc. ...
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... CKE 9Dh ANSEL 86h TRISB Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by the MSSP in SPI mode. 2002 Microchip Technology Inc. PIC16C717/770/771 9.1.8 EFFECTS OF A RESET A RESET disables the MSSP module and terminates the current transfer. Bit 5 ...
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... SSPIF interrupts. Advance Information SLAVE MODE BLOCK DIAGRAM Internal Data Bus Read Write SSPBUF reg Shift Clock SSPSR reg MSb LSb Match detect Addr Match SSPADD reg Set, RESET START and S, P bits STOP bit detect (SSPSTAT reg 2002 Microchip Technology Inc. ...
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... SSP interrupt flag bit; SSPIF (PIR1<3>) is set (interrupt is generated if enabled the falling edge of the ninth SCL pulse. 2002 Microchip Technology Inc. PIC16C717/770/771 9.2.2.2 10-BIT ADDRESSING In 10-bit mode, the basic receive and transmit opera- tions are the same as in the 7-bit mode. However, the criteria for address match are more complex ...
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... Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. NACK is sent because of overflow Advance Information Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes Receiving Data NACK Bus Master terminates transfer 2002 Microchip Technology Inc. ...
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... FIGURE 9- SLAVE MODE FOR RECEPTION (10-BIT ADDRESS) 2002 Microchip Technology Inc. PIC16C717/770/771 Advance Information DS41120B-page 79 ...
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... SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) Advance Information 2 C Slave mode, refer ® SSP R/W 0 Transmitting Data NACK From SSP interrupt service routine 2002 Microchip Technology Inc. ...
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... I FIGURE 9-11: C SLAVE MODE WAVEFORMS FOR TRANSMISSION (10-BIT ADDRESS) 2002 Microchip Technology Inc. PIC16C717/770/771 Advance Information DS41120B-page 81 ...
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... Acknowledge (Figure 9-12). Address is compared to General Call Address after ACK, set interrupt flag R ACK Cleared in software SSPBUF is read Advance Information Receiving data ACK ’0’ ’1’ 2002 Microchip Technology Inc. ...
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... FIGURE 9-13: MSSP BLOCK DIAGRAM (I SDA SDA in SCL SCL in Bus Collision 2002 Microchip Technology Inc. PIC16C717/770/771 9.2.6 MASTER MODE Master mode operation supports interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control ...
Page 86
... FIGURE 9-14: SSPM<3:0> SSPM<3:0> SCL BRG CLKOUT 2 C bus will not 2 C Advance Information C Master mode to set the SCL clock fre- BAUD RATE GENERATOR BLOCK DIAGRAM SSPADD<6:0> Reload Reload Control Fosc/2 BRG Down Counter 2002 Microchip Technology Inc. ...
Page 87
... The baud rate generator is suspended leaving the SDA line held low. • The SSPIF flag is set. FIGURE 9-16: FIRST START BIT TIMING Write to SEN bit occurs here. SDA SCL 2002 Microchip Technology Inc. PIC16C717/770/771 DX-1 SCL allowed to transition high BRG decrements (on Q2 and Q4 cycles) 02h 01h ...
Page 88
... SSPCON2 is disabled until the Repeated START condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here. T BRG Sr = Repeated START Advance Information 1st Bit T BRG 2002 Microchip Technology Inc. ...
Page 89
... SSPBUF leaving SCL low and SDA unchanged (Figure 9-18). 2002 Microchip Technology Inc. PIC16C717/770/771 A typical transmit sequence would go as follows: a) The user generates a START Condition by set- ting the START enable bit (SEN) in SSPCON2 ...
Page 90
... PIC16C717/770/771 2 FIGURE 9-18 MASTER MODE WAVEFORMS FOR TRANSMISSION (7 OR 10-BIT ADDRESS) DS41120B-page 88 Advance Information 2002 Microchip Technology Inc. ...
Page 91
... The user can then send an Acknowledge bit at the end of reception by clearing the ACKDT bit (SSPCON2<5>) and setting the Acknowl- edge sequence enable bit, ACKEN (SSPCON2<4>). 2002 Microchip Technology Inc. PIC16C717/770/771 A typical receive sequence would go as follows: a) The user generates a START Condition by set- ting the START enable bit (SEN) in SSPCON2 ...
Page 92
... PIC16C717/770/771 2 FIGURE 9-19 MASTER WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) DS41120B-page 90 Advance Information 2002 Microchip Technology Inc. ...
Page 93
... SSPIF occurs at the end of receive Note one baud rate generator period. BRG 2002 Microchip Technology Inc. PIC16C717/770/771 arbitration), the baud rate generator is reloaded and counts for another T period, the following events occur (see Figure 9-20): • The SCL pin is pulled low. ...
Page 94
... P bit (SSPSTAT<4>) is set PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG Advance Information ) the STOP condition is complete and 2002 Microchip Technology Inc. ...
Page 95
... Release SCL, Slave device holds SCL low. SCL SDA T BRG 2002 Microchip Technology Inc. PIC16C717/770/771 SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 9-22) ...
Page 96
... Sample SDA. While SCL is high SDA line pulled low by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master Advance Information 2 C bus is free, the user can 2 C Set bus collision interrupt. 2002 Microchip Technology Inc. ...
Page 97
... S bit and SSPIF set because BCLIF SDA = 0, SCL = 1 S SSPIF 2002 Microchip Technology Inc. PIC16C717/770/771 while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ’1’ during the START condition. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 9-26). If however a ’ ...
Page 98
... Bus collision occurs, Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF BRG T BRG s SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SDA = 0, SCL = 1 Set SSPIF Advance Information Interrupts cleared in software. ’0’ ’0’ Interrupts cleared in software. 2002 Microchip Technology Inc. ...
Page 99
... RSEN ’0’ S ’0’ SSPIF 2002 Microchip Technology Inc. PIC16C717/770/771 ’0’). If however SDA is sampled high, then the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time ...
Page 100
... This is another case of another master attempt- ing to drive a data '0' (Figure 9-30 BRG BRG T BRG BRG SCL goes low before SDA goes high Set BCLIF Advance Information SDA sampled T BRG low after T , BRG Set BCLIF ’0’ ’0’ T BRG 2002 Microchip Technology Inc. ...
Page 101
... SSPCON2 GCEN ACKSTAT 94h SSPSTAT SMP CKE 93h SSPADD Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the MSSP in I 2002 Microchip Technology Inc. PIC16C717/770/771 example, with a supply voltage max = function The desired noise margin of 0.1V limits the maximum value of R optional and used to improve ESD susceptibility ...
Page 102
... PIC16C717/770/771 NOTES: DS41120B-page 100 Advance Information 2002 Microchip Technology Inc. ...
Page 103
... Selection of reserved setting may result in an inadvertent interrupt. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 The source for the reference voltages comes from the bandgap reference circuit. The bandgap circuit is ener- gized anytime the reference voltage is required by the other sub-modules, and is powered down when not in use ...
Page 104
... Value at POR DS41120B-page 102 R/W-0 R/W-0 U-0 VRHOEN VRLOEN — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 U-0 U-0 — — — bit 0 output functions REF x = Bit is unknown 2002 Microchip Technology Inc. ...
Page 105
... FIGURE 10-1: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT V DD RA1/AN1/LVDIN LVDEN 2002 Microchip Technology Inc. PIC16C717/770/771 The VRL reference is enabled by setting control bit VRLEN (REFCON<6>). When this bit is set, the gain amplifier is enabled. After a specified start-up time a stable reference of 2.048V nominal is generated and can be used by the A/D converter as a reference input ...
Page 106
... The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when LV<3:0> = 1111. When these bits are set the compar- ator input is multiplexed from an external input pin (RA1/AN1/LVDIN). 2002 Microchip Technology Inc. ...
Page 107
... The PIC16C717 analog-to-digital converter (A/D) allows conversion of an analog input signal to a corre- sponding 10-bit digital value, while the A/D converter in the PIC16C770/771 allows conversion to a corre- sponding 12-bit digital value. The A/D module has analog inputs, which are multiplexed into one sample and hold ...
Page 108
... Legend Readable bit - n = Value at POR DS41120B-page 106 R/W-0 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 GO/DONE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 CHS3 ADON bit Bit is unknown 2002 Microchip Technology Inc. ...
Page 109
... Value at POR The value that is in the ADRESH and ADRESL regis- ters are not modified for a Power-on Reset. The ADRESH and ADRESL registers will contain unknown data after a Power-on Reset. FIGURE 11-1: PIC16C770/771 12-BIT A/D RESULT FORMATS Left Justified MSB (ADFM = 0) bit7 ...
Page 110
... A/D port con- figuration bits (PCFG<3:0>). Unused LSB Unused +), The low refer- REF DD -), external REF SS 2002 Microchip Technology Inc. ...
Page 111
... VOLTAGE A/D VCFG<2:0> C ONVERTER V - REF (R EFERENCE -) VOLTAGE VCFG<2:0> 2002 Microchip Technology Inc. PIC16C717/770/771 4. Wait the required acquisition time. 5. START conversion • Set GO/DONE bit (ADCON0) 6. Wait 13T until A/D conversion is complete either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 7 ...
Page 112
... V > 3.0V time. AD time for V > 3.0V requirement is automatically AD time AD times MHz 1.25 MHz (2) (2) 500 ns 1.6 s 2.0 s 6.4 s (3) (3) 8.0 s 25.6 s (1,4) (1, ( 12 51.2 s (3) (3) ( 204.8 s (4,5) (4,5) (4, 2002 Microchip Technology Inc. . ...
Page 113
... Then the ; conversion may be started. BSF ADCON0, GO ;Start A/D Conversion : ;The ADIF bit will be ;set and the GO/DONE bit : ;cleared upon completion- ;of the A/D conversion. ; Wait for A/D completion and read ADRESH:ADRESL for result. 2002 Microchip Technology Inc. PIC16C717/770/771 DS41120B-page 111 ...
Page 114
... A/D Clock Conversion Delayed = RC? 1 Instruction Cycle No Yes Abort Conversion SLEEP Instruction? ADIF = 0 No SLEEP Finish Conversion Power-down A ADIF = 1 DS41120B-page 112 Yes Finish Conversion SLEEP Instruction? ADIF = 1 No Wake-up Finish Conversion From SLEEP ADIF = 1 Stay in SLEEP Power-down A Yes No 2002 Microchip Technology Inc. ...
Page 115
... This equation assumes that 1/4 LSb error is used (16384 steps for the A/D). The 1/4 LSb error is the maximum error allowed for the A/D to meet its specified resolution. The C is assumed for the 12-bit HOLD A/D. 2002 Microchip Technology Inc. PIC16C717/770/771 EXAMPLE 11- --------------- - – ...
Page 116
... Port Pin PIN Legend C = input capacitance PIN V = threshold voltage leakage current at the pin due to LEAKAGE various junctions R = interconnect resistance sampling switch C = sample/hold capacitance HOLD DS41120B-page 114 V DD Sampling Switch LEAKAGE V = 0.6V T ± 100 HOLD Sampling Switch ( 2002 Microchip Technology Inc. ...
Page 117
... This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRESH and ADRESL registers are not modified. The ADRESH and ADRESL registers will contain unknown data after a Power-on Reset. 2002 Microchip Technology Inc. PIC16C717/770/771 11.9 Faster Conversion - Lower Resolution Trade-off ...
Page 118
... CHS3 ADON 0000 0000 0000 0000 — — 0000 ---- 0000 ---- 000x 0000 000u 0000 xxxx xx11 uuuu uu11 1111 1111 1111 1111 1111 1111 1111 1111 ANS1 ANS0 1111 1111 1111 1111 0000 0000 0000 0000 2002 Microchip Technology Inc. ...
Page 119
... A set of configuration bits are used to select var- ious options. Additional information on special features is available in the PICmicro™ Mid-Range MCU Family Reference Manual, (DS33023). 2002 Microchip Technology Inc. PIC16C717/770/771 12.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations ...
Page 120
... All of the CP bits must be given the same value to enable code protection. Legend R = Readable bit W = Writable bit -n = Value at POR 1 = bit is set DS41120B-page 118 CP — BODEN MCLRE PWRTE WDTE (2) ( Unimplemented bit, read as ‘0’ bit is cleared FOSC2 FOSC1 FOSC0 bit0 x = bit is unknown 2002 Microchip Technology Inc. ...
Page 121
... Note1: See Table 12-1 and Table 12-2 for recom- mended values of C1 and C2 series resistor (RS) may be required for AT strip cut crystals varies with the Crystal mode chosen. 2002 Microchip Technology Inc. PIC16C717/770/771 TABLE 12-1: Mode XT 455 kHz 2.0 MHz 4.0 MHz HS 8 ...
Page 122
... When the speed changes from fast to slow, the processor inactive period is in the range of 100 S to 300 S. For speed change from slow to fast, the pro- cessor is in active for 1. 3.25 S. values. DD See the PCON Register, 2002 Microchip Technology Inc. ...
Page 123
... OSC1 PWRT Dedicated 10-bit Ripple counter Oscillator 2002 Microchip Technology Inc. PIC16C717/770/771 Some registers are not affected in any RESET condi- tion. Their status is unknown on a Power-up Reset and unchanged in any other RESET. Most other registers are placed into an initialized state upon RESET, how- ...
Page 124
... BOR trip point). DD falls below the specified trip point for , (parameter #35), the brown-out situ- BOR . The BOR rises DD drops below V while the Power-up BOR , the Power-up Timer will BOR time delay. Even though the PWRT 2002 Microchip Technology Inc. ...
Page 125
... Brown-out Reset Interrupt wake-up from SLEEP, GIE = 0 Interrupt wake-up from SLEEP, GIE = 1 Legend unchanged unknown unimplemented bit read as '0'. 2002 Microchip Technology Inc. PIC16C717/770/771 Table 12-5 shows the RESET conditions for some spe- cial function registers, while Table 12-6 shows the RESET conditions for all the registers ...
Page 126
... Microchip Technology Inc. ...
Page 127
... See Table 12-5 for RESET value for specific condition. FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2002 Microchip Technology Inc. PIC16C717/770/771 MCLR Reset or Brown-out Reset WDT Reset 0000 0000 0000 0000 0000 ---- 0000 ---- --00 0101 ...
Page 128
... OST TIME-OUT INTERNAL RESET FIGURE 12-9: SLOW V RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET Note 1: Time dependent on oscillator circuit DS41120B-page 126 T PWRT T OST T PWRT T OST ) PWRT (1) T OST ): CASE CASE 2 DD 2002 Microchip Technology Inc. ...
Page 129
... TMR2IF TMR2IE TMR1IF TMR1IE BCLIF BCLIE 2002 Microchip Technology Inc. PIC16C717/770/771 The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the spe- cial function registers PIR1 and PIR2. The correspond- ...
Page 130
... Executes the ISR code. e) Restores the PCLATH register. f) Restores the STATUS register g) Restores W. Note that PCLATH_TEMP are defined in the common RAM area (70h - 7Fh) to avoid register bank switching during con- text save and restore. (INTCON<4>). W_TEMP, STATUS_TEMP and 2002 Microchip Technology Inc. ...
Page 131
... RBPU Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for the full description of the configuration word bits. 2002 Microchip Technology Inc. PIC16C717/770/771 wake-up and continue with normal operation (Watch- dog Timer Wake-up). The TO bit in the STATUS regis- ter will be cleared upon a Watchdog Timer time-out ...
Page 132
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP peripheral can wake the device from SLEEP, then to ensure that the WDT is cleared, a CLRWDT instruc- tion should be executed before a SLEEP instruction. 2002 Microchip Technology Inc. ...
Page 133
... ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are read- able and writable during program/verify recom- mended that only the 4 Least Significant bits of the ID location are used. 2002 Microchip Technology Inc. PIC16C717/770/771 (1) T OST ...
Page 134
... PIC16C717/770/771 NOTES: DS41120B-page 132 2002 Microchip Technology Inc. ...
Page 135
... MHz, the normal instruction execution time conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time 2002 Microchip Technology Inc. PIC16C717/770/771 Table 13-2 lists the instructions recognized by the MPASM™ assembler. Figure 13-1 shows the general formats that the instruc- tions can have ...
Page 136
... TO 00 0000 0110 0011 1 C,DC,Z 11 110x kkkk kkkk 1010 kkkk kkkk 2002 Microchip Technology Inc. Notes 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 ...
Page 137
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. 2002 Microchip Technology Inc. PIC16C717/770/771 ANDWF AND W with f Syntax: [label] ANDWF f,d Operands 127 d Operation: (W) .AND. (f) ...
Page 138
... CLRW None 00h ( register is cleared. Zero bit (Z) is set. Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. 2002 Microchip Technology Inc. ...
Page 139
... W register. If ’d’ the result is placed back in reg- ister ’f’. If the result is 1, the next instruc- tion is executed. If the result is 0, then a NOP is executed instead making instruction. CY 2002 Microchip Technology Inc. PIC16C717/770/771 GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 ...
Page 140
... None The eight bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s. Move label ] MOVWF 127 (W) (f) None Move data from W register to reg- ister 'f'. No Operation [ label ] NOP None No operation None No operation. 2002 Microchip Technology Inc. ...
Page 141
... Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 2002 Microchip Technology Inc. PIC16C717/770/771 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: ...
Page 142
... W register. XORWF Exclusive OR W with f Syntax: [label] XORWF Operands 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2002 Microchip Technology Inc. f,d ...
Page 143
... A project manager • Customizable toolbar and key mapping • A status bar • On-line help 2002 Microchip Technology Inc. PIC16C717/770/771 The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...
Page 144
... ICEPIC In-Circuit Emulator The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards ...
Page 145
... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2002 Microchip Technology Inc. PIC16C717/770/771 14.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...
Page 146
... EE OQ Programming Tools K L evaluation and programming tools support EE OQ Microchip’s HCS Secure Data Products. The HCS eval- uation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters. 2002 Microchip Technology Inc. ...
Page 147
... DEVELOPMENT TOOLS FROM MICROCHIP MCP2510 MCRFXXX HCSXXX 93CXX 25CXX/ 24CXX/ PIC18FXXX PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16C8X PIC16C7XX PIC16C7X PIC16F62X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12CXXX Tools Software Emulators Debugger Programmers 2002 Microchip Technology Inc. PIC16C717/770/771 Kits Eval and Boards Demo DS41120B-page 145 ...
Page 148
... PIC16C717/770/771 NOTES: DS41120B-page 146 2002 Microchip Technology Inc. ...
Page 149
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2002 Microchip Technology Inc. PIC16C717/770/771 (except V , MCLR and RA4) ...
Page 150
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41120B-page 148 4 10 Frequency (MHz Frequency (MHz 2002 Microchip Technology Inc. ...
Page 151
... FIGURE 15-3: PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH, - 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2002 Microchip Technology Inc. PIC16C717/770/771 Frequency (MHz DS41120B-page 149 ...
Page 152
... V/ms See section on Power-on Reset for details. PWRT enabled can be lowered without losing RAM data. T +70°C for commercial A T +85°C for industrial A T +125°C for extended A T +70°C for commercial A T +85°C for industrial A T +125°C for extended A Conditions 2002 Microchip Technology Inc. ...
Page 153
... The test conditions for all I DD OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V MCLR = V ; WDT enabled/disabled as specified. DD 2002 Microchip Technology Inc. PIC16C717/770/771 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C -40°C -40°C ...
Page 154
... A Conditions = 3V, -40°C to 85°C = 3V, -40°C to 125°C = 2.5V, -40°C to 85°C = 2.5V, -40°C to 125°C = 5.5V, -40°C to 85°C = 5.5V, -40°C to 125°C = 4V, -40°C to 85°C = 4V, -40°C to 125° 2002 Microchip Technology Inc. ...
Page 155
... These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2002 Microchip Technology Inc. PIC16C717/770/771 Standard Operating Conditions (unless otherwise stated) Operating temperature 0° ...
Page 156
... V 5.5V DD For entire V range DD For entire V range PIN Pin at hi-impedance PIN Pin at hi-impedance PIN PIN XT, HS, LP and EC PIN DD osc configuration I = 8 -3 RA4 pin nal clock is used to drive OSC1. output enabled RH output enabled RL 2002 Microchip Technology Inc. ...
Page 157
... High I Invalid (Hi-impedance) L Low specifications only) AA output access BUF Bus free High High Low Low specifications only Hold ST DAT DATA input hold STA START condition 2002 Microchip Technology Inc. PIC16C717/770/771 specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period ...
Page 158
... PIC16C717/770/771 FIGURE 15-4: LOAD CONDITIONS Load condition Pin 464 for all pins except OSC2 for OSC2 output DS41120B-page 156 Load condition Pin 2002 Microchip Technology Inc. ...
Page 159
... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken ER or INTRC w/CLKOUT mode where CLKOUT output 2002 Microchip Technology Inc. PIC16C717/770/771 Q1 Q2 ...
Page 160
... LP mode MHz XT mode MHz HS mode kHz LP mode ns XT mode ns EC mode ns HS mode s LP mode ns XT mode ns HS mode s LP mode 4/F CY OSC ns XT mode s LP mode ns HS mode EC mode ns XT mode ns LP mode ns HS mode EC mode 2002 Microchip Technology Inc. ...
Page 161
... Internal RESET Watchdog Timer RESET I/O Pins Note: Refer to Figure 15-4 for load conditions. FIGURE 15-8: BROWN-OUT RESET TIMING V DD 2002 Microchip Technology Inc. PIC16C717/770/771 T +70°C for commercial A -40°C T +85°C for industrial A -40°C T +125°C for extended ...
Page 162
... V BOR Max Units Conditions — 5V, -40°C to +85° 5V, -40°C to +85°C DD — — OSC1 period OSC 132 5V, -40°C to +85°C DD 2.1 s — (D005) DD BOR (device not in Brown-out Reset time-out 48 2002 Microchip Technology Inc. ...
Page 163
... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 15-11: ENHANCED CAPTURE/COMPARE/PWM TIMINGS (ECCP) RB3/CCP1/P1A (Capture Mode) RB3/CCP1/P1A (Compare or PWM Mode) Note: Refer to Figure 15-4 for load conditions. 2002 Microchip Technology Inc. PIC16C717/770/771 Min No Prescaler 0. With Prescaler 10 No Prescaler 0 ...
Page 164
... DS41120B-page 162 Min Typ† Max Units Conditions 0. — CY PIC16C717/770/771 10 — PIC16LC717/770/771 20 — 0. — CY PIC16C717/770/771 10 — PIC16LC717/770/771 20 — — PIC16C717/770/771 — 10 PIC16LC717/770/771 — 25 PIC16C717/770/771 — 10 PIC16LC717/770/771 — 25 — ns — ns — ns — ns — ns — ns — prescale value ( 16 2002 Microchip Technology Inc. ...
Page 165
... Bandgap start-up time BGAP * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2002 Microchip Technology Inc. PIC16C717/770/771 T BGAP Min Typ† Max Units — ...
Page 166
... Max 2.5 2.58 2.66 2.7 2.78 2.86 2.8 2.89 2.98 3.0 3.1 3.2 3.3 3.41 3.52 V 3.5 3.61 3.72 LVD 3.6 3.72 3.84 3.8 3.92 4.04 4.0 4.13 4.26 4.2 4.33 4.46 4.5 4.64 4.78 Units Conditions 2002 Microchip Technology Inc. ...
Page 167
... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2002 Microchip Technology Inc. PIC16C717/770/771 0°C ≤ T ≤ +70°C for commercial A -40° ...
Page 168
... PIC16C717/770/771 15.4.5 A/D CONVERTER MODULE TABLE 15-11: PIC16C770/771 AND PIC16LC770/771 A/D CONVERTER CHARACTERISTICS: Param. Sym Characteristic No. A01 N Resolution R A03 E Integral error IL A04 E Differential error DL A06 E Offset error OFF A07 E Gain Error GN A10 — Monotonicity A20* V Reference voltage REF ( REF REF A21* ...
Page 169
... FIGURE 15-14: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D RC clock source is selected, a time of T instruction to be executed. 2002 Microchip Technology Inc. PIC16C717/770/771 131 130 11 10 ...
Page 170
... PIC16C717/770/771 TABLE 15-12: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENTS (NORMAL MODE) Parameter Sym Characteristic No. (3) T A/D clock period AD 130* 131* T Conversion time CNV (not including acquisition time) (Note 1) 132* T Acquisition Time ACQ 134 A/D clock GO start * These parameters are characterized but not tested. ...
Page 171
... Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D RC clock source is selected, a time of T instruction to be executed. TABLE 15-13: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENT (SLEEP MODE) Parameter Sym Characteristic No. (3) T A/D Internal RC AD 130* oscillator period ...
Page 172
... AIN REF AIN REF Absolute minimum electrical spec to ensure 10-bit accuracy. Min. resolution for A/D is 4.1 mV Min. resolution for A During V acquisition. AIN Based on differential HOLD AIN To charge C see Section 11.0 . HOLD During A/D conversion cycle. 2002 Microchip Technology Inc. ...
Page 173
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 11.6 for minimum conditions. 3: These numbers multiplied 2002 Microchip Technology Inc. PIC16C717/770/771 131 130 9 ...
Page 174
... C ). HOLD — If the A/D RC clock source is selected, a time added CY before the A/D clock starts. This allows the SLEEP instruction to be executed. 2002 Microchip Technology Inc. ...
Page 175
... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 2002 Microchip Technology Inc. PIC16C717/770/771 72 78 ...
Page 176
... PIC16LCXXX — PIC16CXXX — PIC16LCXXX — PIC16CXXX — PIC16LCXXX Typ† Max Units Conditions — — ns — — ns Note 1 — — ns — — ns Note 1 — — ns — — ns Note 1 — — — — 100 ns — — ns 2002 Microchip Technology Inc. ...
Page 177
... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 2002 Microchip Technology Inc. PIC16C717/770/771 72 ...
Page 178
... PIC16LCXXX — PIC16CXXX — PIC16LCXXX — 1. Typ† Max Units Conditions — — ns — — ns — — ns Note 1 — — ns — — ns Note 1 — — ns Note 1 — — — — — 100 ns — — 100 ns — — ns 2002 Microchip Technology Inc. ...
Page 179
... Maximum pin capacitance = 10 pF for all I FIGURE 15-23: MASTER SSP I 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 15-4 for load conditions. 2002 Microchip Technology Inc. PIC16C717/770/771 2 C BUS START/STOP BITS TIMING WAVEFORMS Min Typ Max 2(T )(BRG + 1) — OSC 2(T )(BRG + 1) — ...
Page 180
... Cb is specified to be from 400 Only relevant for Repeated ms START ms condition ms After this period the first clock ms pulse is generated Note Time the bus must be free ms before a new transmission ms can start specification, please refer to the : ) 250 ns must then be met. SU DAT 2002 Microchip Technology Inc. ...
Page 181
... V OSC DD FIGURE 16-1: MAXIMUM I DD 6.0 5.0 4.0 3.0 2.0 1.0 0.0 4.00 6.00 8.00 2002 Microchip Technology Inc. PIC16C717/770/771 VS. F OVER V (HS MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 10.00 12.00 14 ...
Page 182
... MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 10.00 12.00 14.00 F (MHz) OSC VS. F OVER V (XT MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 1.50 2.00 2.50 F (MHz) OSC 16.00 18.00 20.00 3.00 3.50 4.00 2002 Microchip Technology Inc. ...
Page 183
... FIGURE 16-5: MAXIMUM I DD 0.140 0.120 0.100 0.080 0.060 0.040 0.020 0.000 0.02 0.03 0.04 2002 Microchip Technology Inc. PIC16C717/770/771 VS. F OVER V (XT MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 1.50 2.00 2.50 F (MHz) OSC VS ...
Page 184
... OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 0.05 0.06 0.07 F (MHz) OSC VS. F OVER V (EC MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 8.00 10.00 12.00 F (MHz) OSC 0.08 0.09 0.10 14.00 16.00 18.00 20.00 2002 Microchip Technology Inc. ...
Page 185
... FIGURE 16-9: MAXIMUM I DD 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 VS. F OVER V (EC MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 6.00 8.00 10.00 12.00 F ...
Page 186
... DS41120B-page 184 VS. F OVER V (ER MODE) OSC 38 38 100 100 200 200 499 499 3.5 4.0 4.5 V (V) DD VS. V (ER MODE 38 38 100 100 200 200 499 499 3.5 4.0 Vdd (V) V (V) DD 5.0 5.5 4.5 5.0 5.5 2002 Microchip Technology Inc. ...
Page 187
... FIGURE 16-13: TYPICAL I DD 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 VS. V (INTRC 37 kHZ MODE) DD Typ (25 °C) 3.5 4.0 V (Volts) DD VS. V (INTRC 37 kHZ MODE) DD -40 °C 25 °C 85 °C 125 °C 3 ...
Page 188
... DS41120B-page 186 VS. V OVER TEMPERATURE (37 kHZ) OSC DD Max (125 °C) Typ (25 °C) Min(-40° C) 3.5 4.0 4.5 V (V) DD VS. V (INTRC 4 MHz MODE Max (-40 °C) Typ (25 °C) 3.5 4.0 4.5 V (Volts) DD 5.0 5.5 5.0 5.5 2002 Microchip Technology Inc. ...
Page 189
... FIGURE 16-17: INTERNAL RC F 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 VS. V (INTRC 4 MHz MODE) DD 125 °C 85 °C 3.5 4.0 V (Volts) DD VS. V OVER TEMPERATURE (4 MHz) OSC DD Max (125 °C) Typ (25 ° ...
Page 190
... PIC16C717/770/771 FIGURE 16-18: MAXIMUM 0.1 0.01 2.5 3.0 DS41120B-page 188 ° ° VS +125 C) DD +125°C +85°C +25°C 3.5 4.0 V (V) DD -40°C 4.5 5.0 5.5 2002 Microchip Technology Inc. ...
Page 191
... FIGURE 16-19: TYPICAL AND MAXIMUM I 16.0 14.0 12.0 10.0 P 8.0 ' 6.0 4.0 2.0 0.0 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° VS +125 WDT DD Max (-40°C) 3.5 4.0 4.5 V (V) DD ° C) Typ (25°C) 5.0 5.5 DS41120B-page 189 ...
Page 192
... DS41120B-page 190 VS. V (32 KHZ, -40 TMR1 DD Max (-40°C) 3.5 4.0 4.5 V (V) DD ° VS +125 VRL DD Max (125°C) Max (85°C) Typ (25°C) 3.5 4.0 4.5 V (V) DD ° ° +125 C) Typ (25°C) 5.0 5.5 ° C) 5.0 5.5 2002 Microchip Technology Inc. ...
Page 193
... FIGURE 16-23: TYPICAL AND MAXIMUM I 75.0 70.0 65.0 60.0 55 50.0 45.0 40.0 35.0 30.0 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° VS +125 VRH DD Max (125°C) Max (85°C) Typ (25°C) 5.0 V (V) DD ° VS +125 LVD DD Max (125° ...
Page 194
... Max (125°C) Max (85°C) Typ (25°C) 3.5 4.0 V (V) DD ° VS +125 BOR DD Max (125°C) Typ (25°C) SLEEP Device in Sleep 3.0 3.5 4.0 V (V) DD ° C) (LVD TRIP = 4.5V) 4.5 5.0 5.5 ° 2.5V) BOR 4.5 5.0 5.5 2002 Microchip Technology Inc. ...
Page 195
... FIGURE 16-27: V VS 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 5.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° VS +125 BOR DD Max (125 °C) Typ (25 °C) Device in Reset RESET 3.5 4.0 4.5 V (V) DD ° ° +125 ...
Page 196
... DS41120B-page 194 ° ° +125 5.0V) DD Max (125°C) Typ (25°C) Min (-40°C) 10.0 15.0 I (mA) OL ° ° +125 3.0V) DD Min (125°C) Typ (25°C) -6.0 -8.0 -10.0 I (mA) OH 20.0 25.0 Max (-40°C) -12.0 -14.0 -16.0 2002 Microchip Technology Inc. ...
Page 197
... FIGURE 16-31: MINIMUM AND MAXIMUM V 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° ° +125 5.0V) DD Max (-40°C) Typ (25°C) Min (125°C) -10.0 -15.0 I (mA VS. V (TTL INPUT,-40 ...
Page 198
... Min High (-40°C) Max Low (-40°C) Min Low (125°C) 3.5 4.0 4.5 V (V) DD Max (125°C) Max (85°C) Typ (25°C) Min (-40°C) 3.5 4.0 4.5 V (V) DD ° ° +125 C) 5.0 5.5 ° ° (- +125 C) DD 5.0 5.5 2002 Microchip Technology Inc. ...
Page 199
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. PIC16C717/770/771 Example PIC16C717/P 9917017 Example PIC16C717/JW 9905017 Example PIC16C717/SO 9910017 Example PIC16C770/P 9917017 DS41120B-page 197 ...
Page 200
... PIC16C717/770/771 17.1 Package Marking Information (Cont’d) 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 20-Lead CERDIP Windowed XXXXXXXX XXXXXXXX YYWWNNN 20-Lead SOIC XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXX YYWWNNN DS41120B-page 198 Example PIC16C770 20I/SS 9917017 Example PIC16C770/JW 9905017 Example PIC16C771/SO 9910017 2002 Microchip Technology Inc. ...