PIC16C770-I/P Microchip Technology, PIC16C770-I/P Datasheet - Page 82

• Manufacturer Part Number: PIC16C770-I/P
• Description: IC MCU CMOS A/D 2K 20MHZ 20-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of: RoHS Compliant
• Core: PIC
• Processor Series: PIC16C
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 256 B
• Data Rom Size: 256 B
• On-chip Adc: 6 bit
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: Through Hole
• Height: 3.3 mm
• Interface Type: I2C, SPI, SSP
• Length: 26.16 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C770I/P

PIC16C717/770/771
9.2.2.4
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the SSP-
STAT register is set. The received address is loaded
into the SSPBUF register on the falling edge of the
eighth SCL pulse. The ACK pulse will be sent on the
ninth bit, and the SCL pin is held low. The slave module
automatically stretches the clock by holding the SCL
line low so that the master will be unable to assert
another clock pulse until the slave is finished preparing
the transmit data. The transmit data must be loaded
into the SSPBUF register, which also loads the SSPSR
register. The CKP bit (SSPCON<4>) must then be set
to release the SCL pin from the forced low condition.
The eight data bits are shifted out on the falling edges
of the SCL input. This ensures that the SDA signal is
valid during the SCL high time (Figure 9-10).
The ACK or NACK signal from the master-receiver is
latched on the rising edge of the ninth SCL input pulse.
The master-receiver terminates slave transmission by
FIGURE 9-10:
DS41120B-page 80
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
S
SLAVE TRANSMISSION
A7
1
Data in
sampled
A6
2
I
2
C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
Receiving Address
3
A4
4
A3
5
A2
6
(the SSPBUF must be written-to
Set bit after writing to SSPBUF
before the CKP bit can be set)
A1
7
Advance Information
R/W = 1
8
9
ACK
SCL held low
until SSPBUF
is written
sending a NACK. If the SDA line is high (NACK), then
the data transfer is complete. When the NACK is
latched by the slave, the slave logic is RESET which
also resets the R/W bit to ’0’. The slave module then
monitors for another occurrence of the START bit. The
slave firmware knows not to load another byte into the
SSPBUF register by sensing that the buffer is empty
(BF = 0) and the R/W bit has gone low. If the SDA line
is low (ACK), the R/W bit remains high indicating that
the next transmit data must be loaded into the SSPBUF
register.
An MSSP interrupt (SSPIF flag) is generated for each
data transfer byte on the falling edge of the ninth clock
pulse. The SSPIF flag bit must be cleared in software.
The SSPSTAT register is used to determine the status
of the byte transfer.
For more information about the I
to Application Note AN734, “Using the PICmicro
for Slave I
D7
1
SSPBUF is written in software
D6
cleared in software
2
2
Master terminates transmission
C™ Communication”.
by responding with NACK
D5
3
Transmitting Data
D4
4
D3
5
2002 Microchip Technology Inc.
D2
6
From SSP interrupt
service routine
D1
7
2
C Slave mode, refer
D0
8
R/W
NACK
9
0
P
®
SSP