PIC16C770-I/P Microchip Technology, PIC16C770-I/P Datasheet - Page 56

• Manufacturer Part Number: PIC16C770-I/P
• Description: IC MCU CMOS A/D 2K 20MHZ 20-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of: RoHS Compliant
• Core: PIC
• Processor Series: PIC16C
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 256 B
• Data Rom Size: 256 B
• On-chip Adc: 6 bit
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: Through Hole
• Height: 3.3 mm
• Interface Type: I2C, SPI, SSP
• Length: 26.16 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C770I/P

PIC16C717/770/771
TABLE 8-1:
8.1
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 register when an event occurs on
pin CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
8.1.1
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB<3> bit.
8.1.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode. In Asynchronous Counter mode,
the capture operation may not work.
8.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
8.1.4
There are three prescaler settings, specified by bits
CCP1M<3:0>. Whenever the ECCP module is turned
off or the ECCP module is not in Capture mode, the
prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
DS41120B-page 54
Note:
ECCP Mode
Compare
Capture Mode
Capture
PWM
If the RB3/CCP1/P1A pin is configured as
an output, a write to the port can cause a
capture condition.
CCP1 PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
ECCP PRESCALER
ECCP MODE - TIMER
RESOURCE
Timer Resource
Timer1
Timer1
Timer2
EXAMPLE 8-1:
FIGURE 8-1:
8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
• driven High
• driven Low
• toggle output (High to Low or Low to High)
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0>. At the same time, interrupt flag bit
CCP1IF is set.
Changing the ECCP mode select bits to the clear out-
put on Match mode (CCP1M<3.0> = “1000”) presets
the CCP1 output latch to the logic 1 level. Changing the
ECCP mode select bits to the clear output on Match
mode (CCP1M<3:0> = “1001”) presets the CCP1 out-
put latch to the logic 0 level.
8.2.1
The user must configure the CCP1 pin as an output by
clearing the appropriate TRISB bit.
8.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the ECCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
RB3/CCP1/
P1A Pin
CLRF
MOVLW
MOVWF
Note:
Compare Mode
NEW_CAPT_PS ; Load WREG with the
CCP1CON
CCP1CON
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the port data
latch.
edge detect
CCP1 PIN CONFIGURATION
TIMER1 MODE SELECTION
Q’s
Prescaler
³ 1, 4, 16
and
CCP1CON<3:0>
Set flag bit CCP1IF
Changing Between
Capture Prescalers
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
; Turn ECCP module off
; new prescaler mode
; value and ECCP ON
; Load CCP1CON with
; this value
 2002 Microchip Technology Inc.
(PIR1<2>)
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L