PIC16C770-I/P Microchip Technology, PIC16C770-I/P Datasheet - Page 180

• Manufacturer Part Number: PIC16C770-I/P
• Description: IC MCU CMOS A/D 2K 20MHZ 20-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of: RoHS Compliant
• Core: PIC
• Processor Series: PIC16C
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 256 B
• Data Rom Size: 256 B
• On-chip Adc: 6 bit
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: Through Hole
• Height: 3.3 mm
• Interface Type: I2C, SPI, SSP
• Length: 26.16 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C770I/P

PIC16C717/770/771
TABLE 15-22: MASTER SSP I
DS41120B-page 178
Note 1: Maximum pin capacitance = 10 pF for all I
Param.
D102 ‡
100*
101*
102*
103*
106*
107*
109*
No.
110
90*
91*
92*
* These parameters are characterized but not tested. For the value required by the I
‡ These parameters are for design guidance only and are not tested, nor characterized.
2: A Fast mode I
PICmicro
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
[(T
Symbol
T
T
T
T
T
T
SU
T
SU
HD
HD
SU
T
T
HIGH
R
LOW
T
Cb
T
BUF
AA
:
:
:
:
) + (T
R
:
F
STA
DAT
STO
STA
DAT
TM
SU
Mid-Range MCU Family Reference Manual (DS33023).
Characteristic
Clock high time
Clock low time
SDA and SCL
rise time
SDA and SCL
fall time
START condition
setup time
START condition
hold time
Data input
hold time
Data input
setup time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
:
DAT
2
C bus device can be used in a Standard mode I
) = 1000 + 250 = 1250 ns], for 100 kHz mode, before the SCL line is released.
2
C BUS DATA REQUIREMENTS
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
2
C pins.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1Cb
20 + 0.1Cb
TBD‡
4.7 ‡
1.3 ‡
TBD
TBD
Min
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
250
100
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
—
—
—
—
—
—
—
—
0
0
2
C bus system, but (T
1000
3500
1000
Max
300
300
300
300
100
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C specification, please refer to the
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SU
:
DAT
2002 Microchip Technology Inc.
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for Repeated
START
condition
After this period the first clock
pulse is generated
Note 2
Time the bus must be free
before a new transmission
can start
)
250 ns must then be met.
Conditions