PIC16C770-I/P Microchip Technology, PIC16C770-I/P Datasheet - Page 97
![IC MCU CMOS A/D 2K 20MHZ 20-DIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC16C770-I/P
Manufacturer Part Number
PIC16C770-I/P
Description
IC MCU CMOS A/D 2K 20MHZ 20-DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C770-I/P
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC16C
No. Of I/o's
16
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
No. Of
RoHS Compliant
Core
PIC
Processor Series
PIC16C
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Data Ram Size
256 B
Data Rom Size
256 B
On-chip Adc
6 bit
Number Of Programmable I/os
16
Number Of Timers
3 bit
Operating Supply Voltage
2.5 V to 5.5 V
Mounting Style
Through Hole
Height
3.3 mm
Interface Type
I2C, SPI, SSP
Length
26.16 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16C770I/P
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9.2.17.1
During a START condition, a bus collision occurs if:
a)
b)
During a START condition both the SDA and the SCL
pins are monitored.
If:
then:
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
FIGURE 9-24:
2002 Microchip Technology Inc.
SDA
SCL
SEN
S
BCLIF
SSPIF
SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-24).
SCL is sampled low before SDA is asserted low.
(Figure 9-25).
the SDA pin is already low
or the SCL pin is already low,
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 9-24).
BUS COLLISION DURING A START
CONDITION
BUS COLLISION DURING START CONDITION (SDA ONLY)
condition if SDA = 1, SCL=1
Set SEN, enable START
SDA sampled low before
START condition.
S bit and SSPIF set because
SDA = 0, SCL = 1
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1
Advance Information
Set BCLIF.
SSPIF and BCLIF are
cleared in software.
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ’1’ during the START condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-26). If however a ’1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pin is
sampled as ’0’, a bus collision does not occur. At the
end of the BRG count the SCL pin is asserted low.
Note:
PIC16C717/770/771
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, REPEATED
START or STOP conditions.
SSPIF and BCLIF are
cleared in software.
DS41120B-page 95
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