AT89S51-24PC Atmel, AT89S51-24PC Datasheet - Page 14

• Manufacturer Part Number: AT89S51-24PC
• Description: IC 8051 MCU 4K FLASH 40-DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S51-24PC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

14. Program Memory Lock Bits
15. Programming the Flash – Parallel Mode
14
AT89S51
The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed (P)
to obtain the additional features listed in
Table 14-1.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.
If the device is powered up without a reset, the latch initializes to a random value and holds that
value until reset is activated. The latched value of EA must agree with the current logic level at
that pin in order for the device to function properly.
The AT89S51 is shipped with the on-chip Flash memory array ready to be programmed. The
programming interface needs a high-voltage (12-volt) program enable signal and is compatible
with conventional third-party Flash or EPROM programmers.
The AT89S51 code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89S51, the address, data, and control
signals should be set up according to the Flash Programming Modes table
ure 17-1
Data Polling: The AT89S51 features Data Polling to indicate the end of a byte write cycle. Dur-
ing a write cycle, an attempted read of the last byte written will result in the complement of the
written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs,
and the next cycle may begin. Data Polling may begin any time after a write cycle has been
initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output
signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is
pulled high again when programming is done to indicate READY.
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
1
2
3
4
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
and
Program Lock Bits
LB1
Figure
U
P
P
P
Lock Bit Protection Modes
PP
to 12V.
17-2. To program the AT89S51, take the following steps:
LB2
U
U
P
P
LB3
U
U
U
P
Protection Type
No program lock features
MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the Flash memory is disabled
Same as mode 2, but verify is also disabled
Same as mode 3, but external execution is also disabled
Table
14-1.
(Table
2487D–MICRO–6/08
17-1) and
Fig-