AT89S51-24PC Atmel, AT89S51-24PC Datasheet - Page 9

• Manufacturer Part Number: AT89S51-24PC
• Description: IC 8051 MCU 4K FLASH 40-DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S51-24PC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

6. Memory Organization
6.1
6.2
7. Watchdog Timer (One-time Enabled with Reset-out)
7.1
2487D–MICRO–6/08
Program Memory
Data Memory
Using the WDT
Table 5-3.
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S51, if EA is connected to V
are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to
external memory.
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct
and indirect addressing modes. Stack operations are examples of indirect addressing, so the
128 bytes of data RAM are available as stack space.
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every
machine cycle while the oscillator is running. This means the user must reset the WDT at least
AUXR1
–
DPS
Not Bit Addressable
Bit
Data Pointer Register Select
Reserved for future expansion
DPS
0
1
Address = A2H
–
7
AUXR1: Auxiliary Register 1
Selects DPTR Registers DP0L, DP0H
Selects DPTR Registers DP1L, DP1H
–
6
–
5
CC
–
4
, program fetches to addresses 0000H through FFFH
–
3
–
2
Reset Value = XXXXXXX0B
–
1
AT89S51
DPS
0
9