ATMEGA64-16AI Atmel, ATMEGA64-16AI Datasheet - Page 18

IC AVR MCU 64K 16MHZ IND 64-TQFP

ATMEGA64-16AI

Manufacturer Part Number
ATMEGA64-16AI
Description
IC AVR MCU 64K 16MHZ IND 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64-16AI
Manufacturer:
Atmel
Quantity:
10 000
AVR Memories
In-System
Reprogrammable
Flash Program
Memory
2490Q–AVR–06/10
This section describes the different memories in the ATmega64. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega64 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
The ATmega64 contains 64 Kbytes On-chip In-System Reprogrammable Flash memory for pro-
gram storage. Since all AVR instructions are 16 bits or 32 bits wide, the Flash is organized as
32K x 16. For software security, the Flash Program memory space is divided into two sections,
Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega64 Pro-
gram Counter (PC) is 15 bits wide, thus addressing the 32K program memory locations. The
operation of Boot Program section and associated Boot Lock bits for software protection are
described in detail in
“Memory Programming” on page 290
SPI, JTAG, or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 8. Program Memory Map
14.
“Boot Loader Support – Read-While-Write Self-programming” on page
Application Flash Section
Boot Flash Section
contains a detailed description on Flash programming in
$0000
$7FFF
“Instruction Execution Tim-
ATmega64(L)
277.
18

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