ATMEGA64-16AI Atmel, ATMEGA64-16AI Datasheet - Page 22

IC AVR MCU 64K 16MHZ IND 64-TQFP

ATMEGA64-16AI

Manufacturer Part Number
ATMEGA64-16AI
Description
IC AVR MCU 64K 16MHZ IND 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64-16AI
Manufacturer:
Atmel
Quantity:
10 000
EEARH and EEARL –
EEPROM Address
Register
EEDR – EEPROM Data
Register
EECR – EEPROM
Control Register
2490Q–AVR–06/10
• Bits 15..11 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bits 10..0 – EEAR10..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 2
Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 2,048.
The Initial Value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega64 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when EEWE is cleared.
Bit
0x1F (0x3F)
0x1E (0x3E)
Read/Write
Initial Value
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
X
R
7
0
7
0
7
0
EEAR6
R/W
R/W
14
R
X
R
6
0
6
0
6
0
EEAR5
R/W
R/W
13
R
R
5
0
X
5
0
5
0
EEAR4
R/W
R/W
12
R
R
4
0
X
4
0
4
0
EEAR3
EERIE
R/W
R/W
R/W
11
R
X
3
0
3
0
3
0
EEAR10
EEMWE
EEAR2
R/W
R/W
R/W
R/W
10
2
0
X
X
2
0
2
EEAR1
EEAR9
EEWE
R/W
R/W
R/W
R/W
1
0
X
X
X
1
9
1
ATmega64(L)
EEAR8
EEAR0
EERE
LSB
R/W
R/W
R/W
R/W
0
0
X
X
0
0
8
0
EEARH
EEARL
EEDR
EECR
22

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