ATMEGA64-16AI Atmel, ATMEGA64-16AI Datasheet - Page 278

• Manufacturer Part Number: ATMEGA64-16AI
• Description: IC AVR MCU 64K 16MHZ IND 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RWW – Read-While-
Write Section
NRWW – No Read-
While-Write Section
2490Q–AVR–06/10
section that is being programmed (erased or written), not which section that actually is being
read during a Boot Loader software update.
If a Boot Loader software update is programming a page inside the RWW section, it is possible
to read code from the Flash, but only code that is located in the NRWW section. During an ongo-
ing programming, the software must ensure that the RWW section never is being read. If the
user software is trying to read code that is located inside the RWW section (that is, by a
call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown
state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-
tion. The Boot Loader section is always located in the NRWW section. The RWW section Busy
Bit (RWWSB) in the Store Program Memory Control Register (SPMCSR) will be read as logical
one as long as the RWW section is blocked for reading. After a programming is completed, the
RWWSB must be cleared by software before reading code located in the RWW section.
“SPMCSR – Store Program Memory Control Register” on page 281.
RWWSB.
The code located in the NRWW section can be read when the Boot Loader software is updating
a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU
is halted during the entire Page Erase or Page Write operation.
Table 107. Read-While-Write Features
Figure 135. Read-While-Write vs. No Read-While-Write
pointer Address During the
Which Section does the Z-
Programming?
NRWW section
RWW section
Z-pointer
Addresses RWW
Section
Code Located in
NRWW Section
Can be Read During
the Operation
Which Section Can
Read-While-Write
No Read-While-Write
be Read During
Programming?
NRWW section
(RWW) Section
(NRWW) Section
None
Halted?
Is the
CPU
Yes
No
Z-pointer
Addresses NRWW
Section
CPU is Halted
During the Operation
for details on how to clear
ATmega64(L)
Read-While-
Supported?
Write
Yes
No
See
278