DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet
DSPIC30F2010-30I/SO
Specifications of DSPIC30F2010-30I/SO
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DSPIC30F2010-30I/SO Summary of contents
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... Rev. A1 Silicon Errata The dsPIC30F2010 (Rev. A1) samples that you have received conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70118 – “dsPIC30F2010 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...
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... PLL Operation The 4x PLL mode of operation may not function correctly for certain input frequencies. 15. Interrupt Controller – Sequential Interrupts Sequential interrupts after modifying the CPU IPL, interrupt IPL, interrupt enable or interrupt flag may cause an address error trap. 16. 8x PLL Mode If 8x PLL mode is used, the input frequency range is 5-10 MHz instead of 4-10 MHz ...
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... DSP MAC type instruction that performs a read operation of a location in Y data memory. © 2008 Microchip Technology Inc. dsPIC30F2010 2. Module: MAC Class Instructions with +4 Address Modification Sequential MAC class instructions, which prefetch data from Y data space using +4 address modification, will cause an address error trap ...
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... Table 1. The work around for Example 4 is demonstrated in Example 5. DS80186J-page 4 These instructions are identified in Table 1. Example 4 demonstrates a scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F2010 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
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... For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. © 2008 Microchip Technology Inc. dsPIC30F2010 6. Module: Interrupting a REPEAT When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap: 1 ...
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... Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from The counter is loaded with 7 at the end of the DISI instruction. ...
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... None. If ADC event trigger from the INT0 pin is required, initialize SMPI<3:0> to ‘0000’ (interrupt on every conversion). © 2008 Microchip Technology Inc. dsPIC30F2010 13. Module: Watchdog Timer The Watchdog Timer does not function as specified. If the CLRWDT instruction is not executed before the Watchdog Timer is half-expired or ...
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... Module: Interrupt Controller – Sequential Interrupts When an interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap. The generic terms “Interrupt 1” and “Interrupt 2” are used to represent any two enabled dsPIC30F interrupts ...
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... In addition, a global variable can be used to keep track of bit 15, so that when an overflow or underflow condition is present on POSCNT, the variable will toggle bit 15. Example 12 shows the code required for this global variable. // Instead of 0xFFFF // Clear QEI interrupt flag // x=2 for dsPIC30F // x=3 for dsPIC33F dsPIC30F2010 DS80186J-page 9 ...
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... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 13 demonstrates the work around described above would apply to a dsPIC30F2010 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function ...
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... Manual” (DS70046) for more details on performing a clock switch operation. Note: The above work around is recommended for users for whom application hardware changes are possible, and also for users whose includes a 32 kHz LP Oscillator crystal. dsPIC30F2010 or Section 29. “Oscillator” application hardware already ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... None. 23. Module: FRC Internal FRC accuracy is outside the specification documented in “Electrical Characteristics”, Table 22-17 “AC Characteristics: Internal RC Accuracy” of the “dsPIC30F2010 Data Sheet” (DS70118). The actual internal FRC accuracy is: • ±4% for 25°C • ±5% for -40°C and 85°C • ...
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... Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: • MOV.D • Register Indirect Addressing (word or byte mode) with pre/post-decrement Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes ...
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... Port Pin Multiplexed with IC1), and 24 (FRC). Revision H (5/2008) 2 Added silicon issues 25 and 26 (I C), and 27 (Timer). Revision J (9/2008) 2 Replaced issues 20 and with issue 30 (I Added silicon issues 26 (PLL Lock Status Bit), 27 (PSV 2 Operations) and 28-30 (I C). © 2008 Microchip Technology Inc. Removed 2 C), 22 (Motor 2 C). dsPIC30F2010 DS80186J-page 15 ...
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... NOTES: DS80186J-page 16 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...