DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet
DSPIC30F2010-30I/SO
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DSPIC30F2010-30I/SO Summary of contents
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... Silicon Errata and Data Sheet Clarification The dsPIC30F2010 family devices that you have received conform functionally to the current Device Data Sheet (DS70118H), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number CPU Y Data Space 1. CPU MAC Class 2. Instructions with +4 Address Modification CPU 3. DAW.b Instruction PSV — 4. Operations CPU Nested DO 5. Loops CPU 6. REPEAT Loop CPU 7. DISI Instruction Timer 32-bit Mode 8. Output PWM Mode 9 ...
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... C module is enabled, the dsPIC device generates a glitch on the SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. Run-Time Self-Programming (RTSP) operations need to be timed by the application software. Self-timed write operations are not supported. dsPIC30F2010 Affected (1) Revisions ...
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... TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Item Module Feature Number Data Write/Erase 32. EEPROM Operation Program RTSP 33. Flash Operation Memory Data — 34. EEPROM Interrupt — 35. Controller Sleep I Sleep 36. PD Mode Current QEI Timer Gated 37. Accumulation Mode QEI Timer Gated 38. Accumulation Mode ADC Current 39 ...
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... MOV W2, [W0++] ;Perform indirect ;write via W0 to ;address >= 0x900 MAC W4*W5, A, [W10]+=2, W5 ;Perform ;read operation ;using Y-AGU © 2010 Microchip Technology Inc. dsPIC30F2010 Work arounds Work around 1: Insert a NOP between the two instructions as shown in Example 2. EXAMPLE 2: CORRECT RESULTS MOV #0x090A, W0 ...
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... Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using +4 address modification, will cause an address error trap. The trap occurs only when all of the following conditions are true: 1. Two sequential MAC class instructions (or a MAC class instruction executed in a REPEAT or DO loop) that prefetch from Y data space ...
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... Example 4 is demonstrated in © 2010 Microchip Technology Inc. These instructions are identified in Example 4 occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F2010 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 CPB W0, [W1++], W4 ; RLC [W1 ...
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... Module: CPU When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT bit (CORCON<11>) will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C Compiler for dsPIC DSCs ...
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... When these events occur, the Output Compare module will drive the pin low for one instruction cycle (T CY Work around None. However, the user may use a timer interrupt, and write to the associated PORT register to control the pin manually. Affected Silicon Revisions dsPIC30F2010 after the module is enabled ...
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... Module: ADC Sampling multiple channels sequentially using any conversion trigger source other than the auto-convert feature requires the SAMC bits to be non-zero. Therefore, if conditions are all satisfied, the module may not operate as specified: - Multiple S&H channels are sampled sequentially CHPS (ADCON2<9:8>) is not equal to ‘00’ and SIMSAM (ADCON1< ...
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... SET_AND_SAVE_CPU_IPL (save_to RESTORE_CPU_IPL (save_to) © 2010 Microchip Technology Inc. dsPIC30F2010 Work around 2: For C Language Source Code For applications using the C language, MPLAB C Compiler for dsPIC DSCs versions 1.32 and higher, provide several macros for modifying the CPU IPL. The SET_CPU_IPL macro provides the ...
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... For modification of the Interrupt 1 setting, the INTERRUPT_PROTECT macro can be used. This macro disables interrupts before executing the desired expression, as shown in Example macro is not distributed with the compiler. EXAMPLE 12: USING INTERRUPT_PROTECT MACRO #define INTERRUPT_PROTECT ( int save_sr; \ SET_AND_SAVE_CPU_IPL (save_sr, 7);\ x; \ RESTORE_CPU_IPL (save_sr); } (void) 0; ...
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... User's code MAXCNT = 0x7FFF; Motor_Position = POSCNT_b15 + POSCNT; // ... User's code } void __attribute__((__interrupt__)) _QEIInterrupt(void) { IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2010 Microchip Technology Inc. shows the // Instead of 0xFFFF // Clear QEI interrupt flag // x=2 for dsPIC30F // x=3 for dsPIC33F dsPIC30F2010 DS80451E-page 13 ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, implement any of the following three work arounds, depending on the application requirements ...
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... Family Reference Manual” (DS70046) for more details on performing a clock switch operation. Note: The above work around is recommended for users for whom application hardware changes are possible, and also for users whose includes a 32 kHz LP Oscillator crystal. Affected Silicon Revisions dsPIC30F2010 application hardware already DS80451E-page 15 ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... X 23. Module: FRC Internal FRC accuracy is outside the specification documented in “Electrical Characteristics”, Table 22-17 “AC Characteristics: Internal RC Accuracy” of the “dsPIC30F2010 Data Sheet” (DS70118). The actual internal FRC accuracy is: • ±4% for 25°C • ±5% for -40°C and 85°C • ...
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... Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of a PSV page. This only occurs when using the following addressing modes: • MOV.D • Register Indirect Addressing (word or byte mode) with pre/post-decrement Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes ...
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... BCLR T1CON, #TON ...... __T1Interrupt: SETM MyFlag BCLR IFS0, #T1IF RETFIE Affected Silicon Revisions dsPIC30F2010 ® . demonstrates this work around for a ;Clear a flag ;Clear Timer1 ;Turn Timer1 On ;Load NVMCON with ;bit8 set ;Perform Unlock ;sequence ;Set the WR bit ;CPU stalls until ;next interrupt ...
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... Module: Data EEPROM When performing write/erase operations on Data EEPROM, the device automatically times the write/erase operation. For this revision of silicon, this method of timing the erase/write operation is not supported. Note that this erratum does not affect writing to Data EEPROM using a device programmer, such as MPLAB ICD 2 or PRO MATE ...
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... If the application does not use the on-chip A/D converter possible to reduce the I below 0.1 μA. The following additional measures need to be taken in these circumstances the application hardware, the V pin (pin 2) on the dsPIC30F2010 should be connected to the circuit ground (GND the application software, the code sequence shown in Example 20 ...
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... Module: QEI When the TQCS and TQGATE bits in the QEIxCON register are set, the POSCNT counter should not increment but erroneously does, and if allowed to increment to match MAXCNT, a QEI interrupt will be generated. Work around To prevent the erroneous increment of POSCNT while running ...
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... All I/Os are configured as inputs and PD pulled high. LVD, BOR, WDT, etc. are all switched off. © 2010 Microchip Technology Inc. dsPIC30F2010 specifica- IL Standard Operating Conditions: 3.3V and 5.0V (±10%) (unless otherwise stated) -40° ...
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... Controller) and 36 (Sleep Mode). This document replaces the following errata documents: • DS80178, “dsPIC30F2010 Rev. A0 Silicon Errata” • DS80186, “dsPIC30F2010 Rev. A1 Silicon Errata” Rev B Document (7/2009) Updated silicon issue 15 (Interrupt Controller). Added silicon issues 37 (QEI) and 38 (QEI). Rev C Document (2/2010) ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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