DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 8

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

dsPIC30F2010
5. Module: CPU
EXAMPLE 6:
6. Module: CPU
DS80451E-page 8
LOOP1: MOV
LOOP0:
Note:
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT bit (CORCON<11>) will produce unexpected
results. Specifically, the device may continue
executing code within the outer DO loop forever.
This erratum does not affect the operation of the
MPLAB C Compiler for dsPIC DSCs.
Work around
The application should save the DCOUNT Special
Function Register (SFR) prior to entering the inner
DO loop and restore it upon exiting the inner DO
loop. This work around is shown in
Affected Silicon Revisions
When interrupt nesting is enabled (or the NSTDIS
bit (INTCON1<15>) is ‘0’), the following sequence
of events will lead to an address error trap:
1. REPEAT loop is active.
2. An interrupt is generated during the execution
3. The CPU executes the Interrupt Service
4. Within the ISR, when the CPU is executing the
A0
X
of the REPEAT loop.
Routine (ISR) of the source causing the
interrupt.
first instruction cycle of the 3-cycle RETFIE
(Return from Interrupt) instruction, a second
interrupt is generated by a source with a higher
interrupt priority.
.include “p30fxxxx.inc”
.......
DO #CNT1, LOOP0
....
PUSH
DO
....
BTSS
BSET
....
....
POP
...
MOV
A1
For details on the functionality of the EDT bit,
see 2.9.2.4 “Early Termination of the DO
Loop” in Section 2. “CPU” (DS70049) of the
“dsPIC30F Family Reference Manual”.
X
A2
DCOUNT
#CNT2, LOOP1
Flag, #0
CORCON, #EDT;Terminate inner
W1, W5
DCOUNT
W5, W8
X
SAVE AND RESTORE
DCOUNT
A3
X
A4
X
;Outer loop start
;Save DCOUNT
;starts
;DO-loop early
;Inner loop ends
;Restore DCOUNT
;Outer loop ends
;Inner loop
Example
6.
EXAMPLE 7:
EXAMPLE 8:
__T1Interrupt:
__T1Interrupt:
Work around
Processing of Interrupt Service Routines should
be disabled while the RETFIE instruction is being
executed. This may be accomplished in two
different ways:
1. Place a DISI instruction immediately before
2. Immediately prior to executing the RETFIE
Affected Silicon Revisions
PUSH
.......
BCLR
POP
DISI
RETFIE
PUSH
.......
BCLR
MOV.B
MOV.B
POP
RETFIE
A0
X
the RETFIE instruction in all Interrupt Service
Routines of interrupt sources that may be
interrupted by other higher priority interrupt
sources (with priority levels 1 through 6). This
is shown in
this example, a DISI instruction inhibits level 1
through level 6 interrupts for 2 instruction
cycles, while the RETFIE instruction is
executed.
instruction, increase the CPU priority level by
modifying the IPL<2:0> bits (SR<7:5>) to ‘111’
as shown in
interrupts between priority levels 1 through 7.
A1
X
W0
IFS0, #T1IF
W0
#1
W0
IFS0, #T1IF
#0xE0, W0
WREG, SR
W0
A2
;Another interrupt occurs
;here and it is processed
;correctly
;Another interrupt occurs
;here and it is processed
;correctly
X
DISI BEFORE RETFIE
RAISE IPL BEFORE RETFIE
Example 7
Example
;Timer1 ISR
;This line optional
;This line optional
;Timer1 ISR
© 2010 Microchip Technology Inc.
A3
X
A4
8. This will disable all
X
in the Timer1 ISR. In