DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 19

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

30. Module: I
© 2010 Microchip Technology Inc.
Note:
When the I
I2CEN bit in the I2CCON register, the dsPIC DSC
device generates a glitch on the SDA and SCL
pins. This glitch falsely indicates “Communication
Start” to all devices on the I
a bus collision in a multi-master configuration.
Additionally, when the I2CEN bit is set, the S and
P bits of the I
‘0’, respectively, which indicate a “Communication
Start” condition.
Work arounds
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
In a single-master environment, add a delay
between enabling the I
transmission. The delay should be equal to or
greater than the time it takes to transmit two data
bits.
In the multi-master configuration, in addition to the
delay, all other I
nized and wait for the I
before initiating any kind of communication.
Work around 2:
In dsPIC DSC devices in which the I
multiplexed
precedence in the use of the pin, it is possible to
avoid this glitch by enabling the higher priority
module before enabling the I
Use the following procedure to implement this
work around:
1. Enable the higher priority peripheral module
2. Set up and enable the I
3. Disable the higher priority peripheral module
Affected Silicon Revisions
A0
X
that is multiplexed on the same pins as the I
module.
that was enabled in step 1.
Work around 2 works only for devices that
share the SDA and SCL pins with another
peripheral that has a higher precedence
over the port latch, such as the UART. The
priority is shown in the pin diagram
located in the data sheet. For example, if
the SDA and SCL pins are shared with the
UART and SPI pins, and the UART has
higher precedence on the port latch pin.
A1
X
2
2
C
C module is enabled by setting the
2
with
A2
C module are set to values ‘1’ and
X
2
C masters should be synchro-
other
A3
X
2
2
C module and the first data
C module to be initialized
A4
2
2
X
modules
C bus, and can cause
C module.
2
C module.
2
C module is
that
have
2
C
31. Module: Program Flash Memory
EXAMPLE 15:
;The following code example assumes that the
;Write-latches have been pre-loaded and
;Timer1 has been set up to interrupt at the
;end of the programming cycle.
L1: BTSS
__T1Interrupt:
When performing Run-Time Self-Programming
(RTSP) operations on program Flash memory or
write operations on Data EEPROM, the device
automatically times the erase/write operation. For
this revision of silicon, this method of timing the
erase/write operation is not supported.
Note that this erratum does not affect program-
ming Flash memory using a device programmer,
such as MPLAB ICD 2 or PRO MATE
Work around
When updating program Flash memory, the pro-
gramming cycle time must be controlled using an
on-chip timer resource. Setting the TWRI bit
(NVMCON<8>) to a logic ‘1’ enables the program
Flash programming cycle time to be terminated by
the next acknowledged interrupt source. There-
fore, the user must ensure that a single timer is
configured to generate a CPU recognized interrupt
and terminate the programming cycle.
The timer cycle should be set for a value greater
than 2 ms but less than 5 ms.
Example 15
programming operation. A similar work around
may be applied for an erase operation.
Affected Silicon Revisions
CLR
CLR
BSET
DISI
MOV
MOV
MOV
MOV
MOV
MOV
BSET
NOP
NOP
BRA
BCLR
......
SETM
BCLR
RETFIE
A0
X
A1
MyFlag
TMR1
T1CON, #TON
#8
#0X4101, W0
W0, NVMCON
#0X55, W0
W0, NVMKEY
#0XAA, W0
W0, NVMKEY
NVMCON, #WR
MyFlag, #0
L1
T1CON, #TON
MyFlag
IFS0, #T1IF
dsPIC30F2010
demonstrates this work around for a
A2
A3
A4
;Clear a flag
;Clear Timer1
;Turn Timer1 On
;Load NVMCON with
;bit8 set
;Perform Unlock
;sequence
;Set the WR bit
;CPU stalls until
;next interrupt
;Optionally wait
;for flag set
;by Timer1 ISR
;Turn off Timer1
;Continue
;Timer1 ISR
;Set a flag
;Clear T1IF and
;return from ISR
DS80451E-page 19
®
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