DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet
DSPIC30F2010-30I/SO
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DSPIC30F2010-30I/SO Summary of contents
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... Microchip Technology Inc. dsPIC30F2010 Data Sheet High-Performance, 16-bit Digital Signal Controllers DS70118H ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Single-cycle Multiply-Accumulate (MAC) operation • 40-stage Barrel Shifter • Dual data fetch © 2008 Microchip Technology Inc. PIC30F2010 ds Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Program Device Pins Mem. Bytes/ Instructions dsPIC30F2010 28 12K/4K DS70118H-page 4 CMOS Technology: • Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • ...
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... QFN AN2/SS1/CN4/RB2 AN3/INDX/CN5 RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 © 2008 Microchip Technology Inc. MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 6 23 PWM3L/RE4 PWM3H/RE5 OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 FLTA/INT0/SCK1/OCFA/RE8 EMUC2/OC1/IC1/INT1/RD0 1 21 PWM2L/RE2 2 20 PWM2H/RE3 3 19 PWM3L/RE4 dsPIC30F2010 4 18 PWM3H/RE5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 dsPIC30F2010 DS70118H-page 5 ...
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... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU Architecture Overview........................................................................................................................................................ 11 3.0 Memory Organization ................................................................................................................................................................. 21 4.0 Address Generator Units ............................................................................................................................................................ 33 5.0 Interrupts .................................................................................................................................................................................... 39 6.0 Flash Program Memory .............................................................................................................................................................. 45 7.0 Data EEPROM Memory ............................................................................................................................................................. 51 8.0 I/O Ports ..................................................................................................................................................................................... 55 9.0 Timer1 Module ........................................................................................................................................................................... 59 10.0 Timer2/3 Module ........................................................................................................................................................................ 63 11.0 Input Capture Module................................................................................................................................................................. 69 12.0 Output Compare Module ............................................................................................................................................................ 73 13 ...
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... This document contains device specific information of the dsPIC30F2010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance microcontroller (MCU) architecture. Figure 1-1 shows a device block diagram for the dsPIC30F2010 device. © 2008 Microchip Technology Inc. dsPIC30F2010 16-bit DS70118H-page 7 ...
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... FIGURE 1-1: dsPIC30F2010 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Loop Address Latch Control Control Logic Logic Program Memory (12 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
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... ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin. Capture inputs. The dsPIC30F2010 has four capture inputs. The inputs are numbered for consistency with the inputs on larger device variants. Quadrature Encoder Index Pulse input. ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type PGD I/O ST PGC I ST RB0-RB5 I/O ST RC13-RC14 I/O ST RD0-RD1 I/O ST RE0-RE5, I/O ST RE8 RF2, RF3 I/O ST PORTF is a bidirectional I/O port. SCK1 I/O ST SDI1 I ST SDO1 O — SS1 ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2008 Microchip Technology Inc. dsPIC30F2010 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. ...
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... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists 16-bit working registers (W0 through W15 40-bit accumulators (ACCA and ACCB), STATUS Register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC) ...
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... DCOUNT 0 DOSTART DOEND 15 0 CORCON DC IPL2 IPL1 IPL0 SRL dsPIC30F2010 PUSH.S Shadow DO Shadow Legend Working Registers Stack Pointer Limit Register AD0 Program Counter REPEAT Loop Counter DO Loop Counter DO Loop Start Address DO Loop End Address Core Configuration Register Z C STATUS Register ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: • DIVF – 16/16 signed fractional divide • ...
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... Automatic saturation on/off for writes to data memory (SATDW). • Accumulator Saturation mode selection (ACCSAT). Note: For CORCON layout, see Table 3-3. © 2008 Microchip Technology Inc. dsPIC30F2010 A block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-2: DSP INSTRUCTION SUMMARY Algebraic ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70118H-page 16 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u r Logic Zero Backfill © 2008 Microchip Technology Inc. ...
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... The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section 5.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain. dsPIC30F2010 DS70118H-page 17 ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled) ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2008 Microchip Technology Inc. dsPIC30F2010 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 15-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70118H-page 20 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2010 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F2010 Reset - GOTO Instruction Reset - Target Address Reserved Ext. Osc. Fail Trap Address Error Trap Stack Error Trap Arithmetic Warn ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Type Instruction Access User User (TBLPAG<7> TBLRD/TBLWT Configuration (TBLPAG<7> TBLRD/TBLWT Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space Visibility Using ...
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... P<23:16> maps to the destination byte when byte select = 0; The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to Section 6.0 “Flash Program Memory” for details on Flash Programming TBLRDL.W TBLRDL.B (Wn<0> dsPIC30F2010 8 0 TBLRDL.B (Wn<0> DS70118H-page 23 ...
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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... EAs sourced from W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. A data space memory map is shown in Figure 3-6. dsPIC30F2010 Program Space 0x100100 15 0 0x001200 ...
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... FIGURE 3-6: DATA SPACE MEMORY MAP MSB Address 0x0001 SFR Space (Note) 0x07FF 0x0801 512 bytes 0x08FF 0x0901 SRAM Space 0x09FF 0x8001 Optionally Mapped into Program Memory 0xFFFF Note: Unimplemented SFR or SRAM locations read as ‘0’. DS70118H-page 26 16 bits MSB ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR Space (Y Space) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2008 Microchip Technology Inc. dsPIC30F2010 SFR Space Unused Y Space Unused Unused MAC Class Ops Read-Only Indirect EA using W8, W9 ...
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... DATA SPACES The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... MSB is always clear. Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2008 Microchip Technology Inc. dsPIC30F2010 There is a Stack Pointer Limit register (SPLIM) associated with the Stack Pointer ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70118H-page 32 © 2008 Microchip Technology Inc. ...
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... The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). The contents of Wn forms the EA post-modified (incremented or decremented constant value pre-modified (incremented or decremented signed constant value to form the EA. The sum of Wn and Wb forms the EA. The sum of Wn and a literal forms the EA. dsPIC30F2010 DS70118H-page 33 ...
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... MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 where Operand 1 is always a working register (i.e., the Addressing mode can only be register direct), which is referred to as Wb. Operand 2 can register, fetched from data memory, or 5-bit literal. The result location can be either a W register or an address location ...
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... Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2008 Microchip Technology Inc. dsPIC30F2010 4.2.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and an end address be specified and loaded ...
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... FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words DS70118H-page 36 MOV #0x1100,W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address MOV #0x8001,W0 MOV W0,MODCON ...
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... XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer dsPIC30F2010 N bytes, should not be enabled to do this, bit reversed Bit Locations Swapped Left-to-Right ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F2010 device. DS70118H-page 38 Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... For more information on the device instruction set and programming, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). The dsPIC30F2010 has 24 interrupt sources and four processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt ...
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... For example, the PLVD (Low-Voltage Detect) can be given a priority of 7. The INT0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. DS70118H-page 40 TABLE 5-1: dsPIC30F2010 INTERRUPT VECTOR TABLE INT Vector Interrupt Source Number ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2008 Microchip Technology Inc. dsPIC30F2010 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs: • A misaligned data word access is attempted. • A data fetch from an unimplemented data memory location is attempted. • A data access of an unimplemented program memory location is attempted. • An instruction fetch from vector space is attempted ...
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... If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine needed to process the interrupt request. dsPIC30F2010 DS70118H-page 43 ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F2010 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. RTSP may be ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F2010 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70118H-page 50 © 2008 Microchip Technology Inc. ...
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... A TBLRD instruction reads a word at the current program word address. This example uses pointer to data EEPROM. The result is placed in register W4, as shown in Example 7-1. EXAMPLE 7-1: MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , TBLRDL [ dsPIC30F2010 DATA EEPROM READ ; Init Pointer ; read data EEPROM DS70118H-page 51 ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the WR and WREN bits in NVMCON register. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F2010 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...
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... I/O cell (pad) to which they are connected. Table 8-1 shows the formats of the registers for the shared ports, PORTB through PORTF. Output Multiplexers 1 Output Enable 0 1 Output Data dsPIC30F2010 I/O Cell I/O Pad Input Data DS70118H-page 55 ...
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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...
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... TABLE 8-1: dsPIC30F2010 PORT REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — ...
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... NOTES: DS70118H-page 58 © 2008 Microchip Technology Inc. ...
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... The dsPIC DSC devices contain up to eight capture channels, (i.e., the maximum value 8). Note: The dsPIC30F2010 device has four capture inputs – IC1, IC2, IC7 and IC8. The naming of these four capture channels is intentional and preserves software compatibility with other dsPIC DSC devices ...
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... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM< ...
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... Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. © 2008 Microchip Technology Inc. dsPIC30F2010 9.2.2 INPUT CAPTURE IN CPU IDLE MODE CPU Idle mode allows input capture module operation with full functionality. In the CPU Idle mode, the interrupt mode selected by the ICI< ...
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TABLE 9-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... Interrupt on 16-bit period register match or falling edge of external gate signal © 2008 Microchip Technology Inc. dsPIC30F2010 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 10- 1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... FIGURE 10-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 10.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...
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... XTAL SOSCO pF 100K © 2008 Microchip Technology Inc. dsPIC30F2010 10.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal the value specified in the period register, and is then Reset to ‘0’. ...
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TABLE 10-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer ...
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... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F2010 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 11-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
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... Reset 0 T3IF Event Flag 1 TGATE See NOTE Note: The dsPIC30F2010 does not have an external pin input to TIMER3. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2008 Microchip Technology Inc. dsPIC30F2010 PR2 TMR2 Q D TGATE ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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TABLE 11-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70118H-page 72 © 2008 Microchip Technology Inc. ...
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... TMR2<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1and 2. © 2008 Microchip Technology Inc. dsPIC30F2010 The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 12.2 Simple Output Compare Match Mode When control bits OCM< ...
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... IFS0 status register, and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (T2IE or T3IE), located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation. in the dsPIC30F2010 DS70118H-page 75 ...
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TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — OCFRZ OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — OCFRZ OCSIDL — Legend: ...
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... TQCKPS<1:0> TQCS QEIM<2:0> TQGATE CK Q 16-bit Up/Down Counter (POSCNT) 2 Quadrature Encoder Interface Logic Comparator/ Zero Detect 3 QEIM<2:0> Mode Select Max Count Register (MAXCNT) dsPIC30F2010 for several motor control bits QEIM<2:0> (QEICON<10:8>). 2 Prescaler 1, 8, 64, 256 QEIIF Event Flag Reset Equal DS70118H-page 77 ...
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... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...
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... To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2008 Microchip Technology Inc. dsPIC30F2010 13.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode QEIM< ...
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... QEI Module Operation During CPU Idle Mode Since the QEI module can function as a quadrature encoder interface 16-bit timer, the following section describes operation of the module in both modes. 13.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI ...
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TABLE 13-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB DFLTCON 0124 — — — — — POSCNT 0126 ...
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... NOTES: DS70118H-page 82 © 2008 Microchip Technology Inc. ...
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... Six PWM I/O pins with three duty cycle generators • 16-bit resolution • ‘On-the-Fly’ PWM frequency changes © 2008 Microchip Technology Inc. dsPIC30F2010 • Edge and Center-Aligned Output modes • Single Pulse Generation mode • Interrupt support for asymmetrical updates in Center-Aligned mode • ...
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... FIGURE 14-1: PWM BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 FLTACON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM Time Base Note: Details of PWM Generator 1 and 2 not shown for clarity. DS70118H-page 84 PWM Enable and Mode SFRs Dead-Time Control SFR ...
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... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2008 Microchip Technology Inc. dsPIC30F2010 14.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...
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... DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional functions to the user ...
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... PTMR Value 0 Duty Cycle Period © 2008 Microchip Technology Inc. dsPIC30F2010 14.4 Center-Aligned PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Counting mode (see Figure 14-3). The PWM compare output is driven to the active state ...
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... DUTY CYCLE REGISTER BUFFERS The four PWM duty cycle registers are double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle, there is a duty cycle register that is accessible by the user and a second duty cycle register that holds the actual compare value used in the present PWM period ...
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... PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2008 Microchip Technology Inc. dsPIC30F2010 14.10 PWM Output Override The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
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... PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control: • HPOL Configuration bit • LPOL Configuration bit • PWMPIN Configuration bit These three bits in the FBORPOR Configuration register (see Section 19.6 “ ...
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... Any write to the SEVTCMP register • Any device Reset © 2008 Microchip Technology Inc. dsPIC30F2010 14.15 PWM Operation During CPU Sleep Mode The FLTA input pin has the ability to wake the CPU from Sleep mode. The PWM module generates an interrupt if the FLTA pin is driven low while in Sleep ...
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TABLE 14-1: PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA — ...
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... SPIxSR. 15.1.2 SDOx DISABLE A control bit, DISSDO, is provided to the SPIxCON register to allow the SDOx output to be disabled. This will allow the SPI module to be connected in an input only configuration. SDO can also be used for general purpose I/O. dsPIC30F2010 /4). This OSC DS70118H-page 93 ...
Page 94
... Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit FRMEN enables framed SPI support and causes the SSx pin to perform the frame synchronization pulse (FSYNC) function. The control bit SPIFSD determines whether the SSx ...
Page 95
... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been de-asserted in the middle of a transmit/receive. © 2008 Microchip Technology Inc. dsPIC30F2010 15.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down. If ...
Page 96
TABLE 15-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, read ...
Page 97
... Following a Restart condition in 10-bit mode, the user only needs to match the first 7-bit address. bit 7 bit 0 bit 7 bit 0 bit 8 bit 0 bit 0 bit 0 bit 9 bit 0 dsPIC30F2010 2 C MODES 2 C operation are supported MODE pulse is generated. During I2CRCV (8 bits) I2CTRN (8 bits) I2CBRG (9 bits) ...
Page 98
... TM FIGURE 16- BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70118H-page 98 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down ...
Page 99
... ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F2010 16.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 100
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as "PRIOR_ADDR_MATCH"), the master can begin sending data bytes for a slave reception operation. 16.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 101
... Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2008 Microchip Technology Inc. dsPIC30F2010 16.10 General Call Address Support The general call address can address all devices. When this address is used, all devices should, in theory, respond with an acknowledgement ...
Page 102
... I C Master Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
Page 103
... Control of the I bus can be taken when the P bit is set in the I2CSTAT register, or the bus is Idle and the S and P bits are cleared. © 2008 Microchip Technology Inc. dsPIC30F2010 2 16. Module Operation During CPU Sleep and Idle Modes 2 16 ...
Page 104
TABLE 16-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...
Page 105
... Family Reference Manual” (DS70046). This section describes the Universal Asynchronous Receiver/Transmitter Communications module. Note: Since dsPIC30F2010 devices have only one UART, all references to Ux... imply that only. FIGURE 17-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus ...
Page 106
... FIGURE 17-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Note only. DS70118H-page 106 Internal Data Bus 16 Read Write UxRXREG Low Byte ...
Page 107
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F2010 17.3 Transmitting Data 17.3.1 TRANSMITTING IN 8-BIT DATA MODE ...
Page 108
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to the Transmit Shift register (UxTSR) ...
Page 109
... Microchip Technology Inc. dsPIC30F2010 17.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...
Page 110
... UART Operation During CPU Sleep and Idle Modes 17.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shutdown and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘ ...
Page 111
TABLE 17-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 112
... NOTES: DS70118H-page 112 © 2008 Microchip Technology Inc. ...
Page 113
... The block diagram of the ADC module is shown in Figure 18-1. / the CH1 S/H - 10-bit Result + CH2 S CH3 S/H CH1,CH2, - CH3,CH0 Sample Input Switches + CH0 S/H - dsPIC30F2010 SSRC<2:0>, ASAM, SIMSAM, ADC Conversion Logic 16-word, 10-bit Dual Port Buffer Sample/Sequence Control Input MUX Control DS70118H-page 113 ...
Page 114
... A/D Result Buffer The module contains a 16-word dual port read-only buf- fer, called ADCBUF0...ADCBUFF, to buffer the ADC results. The RAM is 10 bits wide, but is read into different format 16-bit words. The contents of the sixteen ADC conversion result buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 115
... Example 18-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. EXAMPLE 18- ADCS<5:0> cycles to AD Therefore, Set ADCS<5:0> Actual T wait is AD dsPIC30F2010 . The source of the A/D CONVERSION CLOCK * (0.5 * (ADCS<5:0> ADCS<5:0> – time AD = 5V). Refer to Section 22.0 ...
Page 116
... ADC VOLTAGE REFERENCE SCHEMATIC μF dsPIC30F2010 μ A/D Channels Configuration REF REF CH1, CH2 or CH3 ...
Page 117
... For example, four inputs can be sampled at a rate of 150 ksps for each signal or two inputs can be sampled at a rate of 300 ksps for each signal. Sequential sampling must be used in this configuration to allow adequate sampling time on each input dsPIC30F2010 + and V - pins following REF REF 1 = 95. ...
Page 118
... Configuration Items The following configuration items are required to achieve a 600 ksps conversion rate. • Comply with conditions provided in Table 18-2 • Connect external V + and V - pins following REF REF the recommended circuit shown in Figure 18-2 • Set SSRC<2:0> = 111 in the ADCON1 register to enable the auto-convert option • ...
Page 119
... Each of the output formats translates to a 16-bit result on the data bus. Write data will always be in right justified (integer) format. d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 dsPIC30F2010 ...
Page 120
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (V will be converted ...
Page 121
TABLE 18-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ...
Page 122
... NOTES: DS70118H-page 122 © 2008 Microchip Technology Inc. ...
Page 123
... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F2010 19.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 124
... TABLE 19-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2 PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled ...
Page 125
... FIGURE 19-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F2010 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer Switching and Control ...
Page 126
... Oscillator Configurations 19.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> Configuration bits that select one of four oscillator groups. b) AND FPR<3:0> Configuration bits that select one of 13 oscillator choices within the primary group. ...
Page 127
... PWRT expires. Note 1: OSC2 pin function is determined by the Primary (FPR<3:0>). 2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all times. dsPIC30F2010 FRC TUNING FRC Frequency + 10.5% + 9.0% + 7.5% + 6. ...
Page 128
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (Clock Switch and Monitor Selection bits) in the F Configuration register. If the FSCM function is ...
Page 129
... Reset The dsPIC30F2010 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Reset cause by trap lockup (TRAPR) h) Reset caused by illegal opcode using an ...
Page 130
... FIGURE 19-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 19-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 131
... The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2008 Microchip Technology Inc. dsPIC30F2010 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 132
... Table 19-5 shows the Reset conditions for the RCON Register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 19-5: ...
Page 133
... If FSCM is not enabled, then the device will simply suspend execution of code until the clock is stable, and will remain in Sleep until the oscillator clock has started. dsPIC30F2010 and T delays are applied. PWRT . PWRT delay and OST timer POR ...
Page 134
... All Resets will wake-up the processor from Sleep mode. Any Reset, other than POR, will set the Sleep status bit POR, the Sleep bit is cleared. If Watchdog Timer is enabled, then the processor will wake-up from Sleep mode upon WDT time-out. The Sleep and WDTO status bits are both set ...
Page 135
TABLE 19-7: SYSTEM INTEGRATION REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR BGST — OSCCON 0742 TUN3 TUN2 COSC<1:0> Legend: — = unimplemented bit Note: Refer to “dsPIC30F Family Reference Manual” ...
Page 136
... NOTES: DS70118H-page 136 © 2008 Microchip Technology Inc. ...
Page 137
... All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. dsPIC30F2010 DS70118H-page 137 ...
Page 138
... Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the ...
Page 139
... Y data space prefetch address register for DSP instructions Wy ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F2010 Description DS70118H-page 139 ...
Page 140
... TABLE 20-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 141
... DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd © 2008 Microchip Technology Inc. dsPIC30F2010 # of Description word Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set ...
Page 142
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R Ws,Wnd 38 GOTO GOTO Expr GOTO Wn 39 INC INC f INC f,WREG INC Ws,Wd 40 INC2 INC2 f INC2 f,WREG INC2 ...
Page 143
... SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd © 2008 Microchip Technology Inc. dsPIC30F2010 # of Description word Negate Accumulator WREG = Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W( Pop Shadow Registers Push f to Top-of-Stack (TOS) ...
Page 144
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 72 SUB SUB Acc SUB f SUB f,WREG SUB #lit10,Wn SUB Wb,Ws,Wd SUB Wb,#lit5,Wd 73 SUBB SUBB f SUBB f,WREG SUBB #lit10,Wn SUBB Wb,Ws,Wd SUBB Wb,#lit5,Wd 74 SUBR SUBR f SUBR f,WREG SUBR Wb,Ws,Wd ...
Page 145
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F2010 21.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 146
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 147
... PC via an RS-232 or USB cable. ® Flash DSCs The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. dsPIC30F2010 run-time development tool, TM (ICSP TM ...
Page 148
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 149
... Microchip Technology Inc. (except V and MCLR) ................................................... -0. (Note 1) ......................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latchup dsPIC30F2010-30I 30 — 20 — 10 dsPIC30F2010 + 0.3V) DD pin, rather PP Max MIPS dsPIC30F2010-20E — 20 — 15 — DS70118H-page 149 ...
Page 150
... TABLE 22-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F2010-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F2010-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: ∑ × – I INT I/O Pin power dissipation: ∑ × ...
Page 151
... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F2010 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 152
... TABLE 22-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter Typical Max No. (1) Operating Current ( DC51a 1.5 3.0 DC51b 1.5 3.0 DC51c 1.5 3.0 DC51e 4.1 7 DC51f 3.6 7 DC51g 3.5 7 DC50a 3 5 DC50b 3 5 DC50c 3 5 DC50e 7 9 DC50f 6 9 DC50g 6 9 DC43a ...
Page 153
... The Δ current is the additional current consumed when the module is enabled. This current should be 2: added to the base I current. PD © 2008 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
Page 154
... TABLE 22-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No Input Low Voltage DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 155
... V – 0.7 — — 0.2 — — – 0.7 — — 0.1 — — DD — — 15 — — 50 — — 400 BO15 Power Up Time-out dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA ...
Page 156
... TABLE 22-10: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. (2) BO10 V BOR Voltage BOR V transition high to DD low BO15 V BHYS Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. ...
Page 157
... Section 22.1 “DC DD Characteristics”. Load Condition 2 - for OSC2 Pin 464 Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended OS31 OS31 OS41 DS70118H-page 157 ...
Page 158
... TABLE 22-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OS10 F External CLKI Frequency OSC (External clocks allowed only in EC mode) Oscillator Frequency OS20 1/F OSC OSC OSC OS25 T Instruction Cycle Time CY (2) OS30 TosL, External Clock in (OSC1) TosH High or Low Time ...
Page 159
... T — 0.632 0.956 % -40°C ≤ T — 0.632 0.956 % dsPIC30F2010 ≤ +85°C for Industrial ≤ +125°C for Extended Units Conditions MHz EC with 4x PLL MHz EC with 8x PLL MHz EC with 16x PLL MHz XT with 4x PLL MHz XT with 8x PLL ...
Page 160
... TABLE 22-16: INTERNAL CLOCK TIMING EXAMPLES Clock F OSC Oscillator T CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle). TABLE 22-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 161
... Measurements are taken in RC mode and EC mode where CLKO output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2008 Microchip Technology Inc. dsPIC30F2010 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 162
... FIGURE 22-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 22-2 for load conditions. ...
Page 163
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 22-1 and Table 22-10 for BOR. © 2008 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 164
... FIGURE 22-6: BAND GAP START-UP TIME CHARACTERISTICS 0V Enable Band Gap (see Note) Note: Band Gap is enabled when FBORPOR<7> is set. TABLE 22-21: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 165
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2008 Microchip Technology Inc. dsPIC30F2010 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 166
... TABLE 22-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment TABLE 22-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS ...
Page 167
... TQ20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F2010 TQ11 TQ10 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 168
... FIGURE 22-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 22-2 for load conditions. TABLE 22-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
Page 169
... Microchip Technology Inc. OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max Units — — — — ns dsPIC30F2010 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions — — DS70118H-page 169 ...
Page 170
... FIGURE 22-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS FLTA/B MP20 PWMx FIGURE 22-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS PWMx Note: Refer to Figure 22-2 for load conditions. TABLE 22-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
Page 171
... T Operating temperature -40°C ≤ T (1) (2) Typ Max 6 T — — — — — — CY dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) DS70118H-page 171 ...
Page 172
... FIGURE 22-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ51 Index Internal Position Coun- TABLE 22-31: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ50 TqIL Filter Time to Recognize Low, with Digital Filter TQ51 ...
Page 173
... Data Input 20 — X Data Input 20 — X dsPIC30F2010 SP20 SP21 LSb LSb IN -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns ...
Page 174
... FIGURE 22-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) SDO MSb X SP40 SDI X MSb IN SP41 Note: Refer to Figure 22-2 for load conditions. TABLE 22-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
Page 175
... Data Input 20 — X Data Input 20 — X ↓ Input 120 — X Output 10 — (3) 1.5 T +40 — CY dsPIC30F2010 SP52 SP72 SP73 LSb SP51 LSb IN -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns ...
Page 176
... FIGURE 22-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 22-2 for load conditions. DS70118H-page 176 SP70 SP72 SP73 SP35 SP73 SP72 ...
Page 177
... Data Input 20 — X Data Input 20 — X ↑ input 120 — — (4) Edge 1 — — — dsPIC30F2010 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns See parameter DO32 — ns ...
Page 178
... FIGURE 22-20: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 22-2 for load conditions. 2 FIGURE 22-21: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 ...
Page 179
... C™ Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ C)” in the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2008 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 180
... FIGURE 22-22: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS30 SDA Start Condition 2 FIGURE 22-23: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70118H-page 180 IS33 IS11 IS10 ...
Page 181
... MHz mode 0.5 — — 400 2 C™ pins (for 1 MHz mode only). dsPIC30F2010 Units Conditions μs Device must operate at a minimum of 1.5 MHz μs Device must operate at a minimum of 10 MHz. μs μs Device must operate at a minimum of 1.5 MHz μ ...
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... TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol Characteristic No. AD01 AV Module V Supply DD DD AD02 AV Module V Supply SS SS AD05 V Reference Voltage High REFH AD06 V Reference Voltage Low REFL AD07 V Absolute Reference Voltage REF AD08 I Current Drain REF AD10 V -V Full-Scale Input Span ...
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... The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 3: Measurements were taken with external V © 2008 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min. ...
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... FIGURE 22-24: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution SET SAMP CLEAR SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 T SAMP DONE ADIF ADRES(0) ADRES( – Software sets ADCON. SAMP to start sampling. ...
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... Software sets ADCON. ADON to start AD operation. 2 – Sampling starts after discharge period described in Section 17. “10-bit A/D Converter” SAMP of the ”dsPIC30F Family Reference Manual” (DS70046). 3 – Convert bit 9. 4 – Convert bit 8. © 2008 Microchip Technology Inc. dsPIC30F2010 AD55 AD55 – ...
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... TABLE 22-39: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. AD50 T A/D Clock Period AD AD51 t A/D Internal RC Oscillator Period RC AD55 t Conversion Time CONV AD56 F Throughput Rate CNV AD57 T Sample Time SAMP AD60 t Conversion Start from Sample PCS Trigger ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. dsPIC30F2010 Example dsPIC30F2010 e -30I/MM 3 060700U Example dsPIC30F2010-30I/SP e 0648017 3 Example dsPIC30F2010-30I/SO e 0648017 DS70118H-page 187 ...
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... DS70118H-page 188 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2010 DS70118H-page 189 ...
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... DS70118H-page 190 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2010 α φ β DS70118H-page 191 ...
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... NOTES: DS70118H-page 192 © 2008 Microchip Technology Inc. ...
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... Revision G (December 2006) This revision includes updates to the packaging diagrams. © 2008 Microchip Technology Inc. dsPIC30F2010 Revision H (May 2008) This revision reflects these updates: • Changed the location of the input reference in the 10-bit High-Speed ADC Functional Block Diagram (see Figure 18-1) • ...
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... NOTES: DS70118H-page 194 © 2008 Microchip Technology Inc. ...
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... Sequence Table (16-Entry)......................................... 38 Block Diagram PWM ........................................................................... 84 © 2008 Microchip Technology Inc. dsPIC30F2010 Block Diagrams 10-bit High Speed ADC Functional........................... 113 16-bit Timer1 Module.................................................. 60 DSP Engine ................................................................ 16 dsPIC30F2010.............................................................. 8 External Power-on Reset Circuit .............................. 131 .............................................................................. 98 Input Capture Mode.................................................... 69 Oscillator System...................................................... 125 Output Compare Mode ............................................... 73 Quadrature Encoder Interface .................................... 77 Reset System ...
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... Spaces ........................................................................ 28 Width ........................................................................... 28 Data EEPROM Memory ...................................................... 51 Erasing ........................................................................ 52 Erasing, Block ............................................................. 52 Erasing, Word ............................................................. 52 Protection Against Spurious Write .............................. 54 Reading....................................................................... 51 Write Verify ................................................................. 54 Writing ......................................................................... 53 Writing, Block .............................................................. 54 Writing, Word .............................................................. 53 DC Characteristics ............................................................ 149 BOR .......................................................................... 156 Brown-out Reset ....................................................... 155 I/O Pin Input Specifications ....................................... 153 I/O Pin Output Specifications .................................... 155 Idle Current (I ) ...
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... MPLAB REAL ICE In-Circuit Emulator System................. 147 MPLINK Object Linker/MPLIB Object Librarian ................ 146 O OC/PWM Module Timing Characteristics.......................... 169 Operating Current (I )..................................................... 151 DD Operating MIPS vs Voltage dsPIC30F2010 .......................................................... 149 Oscillator Configurations Fast RC (FRC) .................................................. 127 Low Power RC (LPRC) ..................................... 127 Phase Locked Loop (PLL) ................................ 127 Oscillator Configurations ................................................... 126 Fail-Safe Clock Monitor............................................. 128 Initial Clock Source Selection ...
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... PWM Register Map............................................................... 92 PWM Duty Cycle Comparison Units ................................... 87 Duty Cycle Register Buffers ........................................ 88 PWM FLTA Pins.................................................................. 90 Enable Bits .................................................................. 90 Fault States ................................................................. 90 Modes ......................................................................... 90 Cycle-by-Cycle.................................................... 90 Latched ............................................................... 90 PWM Operation During CPU Idle Mode.............................. 91 PWM Operation During CPU Sleep Mode .......................... 91 PWM Output and Polarity Control ....................................... 90 Output Pin Control ...................................................... 90 PWM Output Override ...
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... Motor Control PWM Module...................................... 170 Oscillator Start-up Timer ........................................... 163 Output Compare Module........................................... 168 Power-up Timer ........................................................ 163 QEI Module External Clock................................................... 167 © 2008 Microchip Technology Inc. dsPIC30F2010 Index Pulse....................................................... 172 Quadrature Decoder................................................. 171 Reset ........................................................................ 163 Simple OC/PWM Mode ............................................ 169 SPI Module Master Mode (CKE = 0).................................... 173 Master Mode (CKE = 1) ...
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... NOTES: DS70118H-page 200 © 2008 Microchip Technology Inc. ...