DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 78

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

dsPIC30F2010
13.1
A typical incremental (a.k.a. optical) encoder has three
outputs: Phase A, Phase B, and an index pulse. These
signals are useful and often required in position and
speed control of ACIM and SR motors.
The two channels, Phase A (QEA) and Phase B (QEB),
have a unique relationship. If Phase A leads Phase B,
then the direction (of the motor) is deemed positive or
forward. If Phase A lags Phase B, then the direction
(of the motor) is deemed negative or reverse.
A third channel, termed index pulse, occurs once per
revolution and is used as a reference to establish an
absolute position. The index pulse coincides with
Phase A and Phase B, both low.
13.2
The 16-bit Up/Down Counter counts up or down on
every count pulse, which is generated by the difference
of the Phase A and Phase B input signals. The counter
acts as an integrator, whose count value is proportional
to position. The direction of the count is determined by
the UPDN signal, which is generated by the
Quadrature Encoder Interface Logic.
13.2.1
Position count error checking in the QEI is provided for
and indicated by the CNTERR bit (QEICON<15>). The
error checking only applies when the position counter
is configured for Reset on the Index Pulse modes
(QEIM<2:0> = ‘110’ or ‘100’). In these modes, the
contents of the POSCNT register is compared with the
values (0xFFFF or MAXCNT + 1, depending on
direction). If these values are detected, an error
condition is generated by setting the CNTERR bit and
a QEI count error interrupt is generated. The QEI count
error interrupt can be disabled by setting the CEID bit
(DFLTCON<8>). The position counter continues to
count encoder edges after an error has been detected.
The POSCNT register continues to count up/down until
a natural rollover/underflow. No interrupt is generated
for the natural rollover/underflow event. The CNTERR
bit is a read/write bit and reset in software by the user.
DS70118H-page 78
Quadrature Encoder Interface
Logic
16-bit Up/Down Position Counter
Mode
POSITION COUNTER ERROR
CHECKING
13.2.2
The Position Counter Reset Enable bit, POSRES
(QEI<2>) controls whether the position counter is reset
when the index pulse is detected. This bit is only
applicable when QEIM<2:0> = ‘100’ or ‘110’.
If the POSRES bit is set to ‘1’, then the position counter
is reset when the index pulse is detected. If the
POSRES bit is set to ‘0’, then the position counter is not
reset when the index pulse is detected. The position
counter will continue counting up or down, and will be
reset on the rollover or underflow condition.
When selecting the INDX signal to reset the position
counter (POSCNT), the user has to specify the states
on QEA and QEB input pins. These states have to be
matched in order for a reset to occur. These states are
selected by the IMV<1:0> bit in the DFLTCON <10:9>
register.
The IMV<1:0> (Index Match Value) bit allows the user
to specify the state of the QEA and QEB input pins
during an index pulse when the POSCNT register is to
be reset.
In 4X Quadrature Count Mode:
IMV1 = Required state of phase B input signal for
IMV0 = Required state of phase A input signal for
In 2X Quadrature Count Mode:
IMV1 = Selects phase input signal for index state
IMV0 = Required state of the selected phase input
The interrupt is still generated on the detection of the
index pulse and not on the position counter over-
flow/underflow.
13.2.3
As mentioned in the previous section, the QEI logic
generates
relationship between Phase A and Phase B. In
addition to the output pin, the state of this internal
UPDN signal is supplied to a SFR bit UPDN
(QEICON<11>) as a read-only bit.
Note:
match on index pulse
match on index pulse
match (0 = Phase A, 1 = Phase B)
signal for match on index pulse
POSITION COUNTER RESET
COUNT DIRECTION STATUS
QEI pins are multiplexed with analog
inputs. User must insure that all QEI
associated pins are set as digital inputs in
the ADPCFG register.
an
UPDN
© 2008 Microchip Technology Inc.
signal,
based
upon
the