DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 90

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

dsPIC30F2010
14.11 PWM Output and Polarity Control
There are three device Configuration bits associated
with the PWM module that provide PWM output pin
control:
• HPOL Configuration bit
• LPOL Configuration bit
• PWMPIN Configuration bit
These three bits in the FBORPOR Configuration
register (see Section 19.6 “Device Configuration
Registers”) work in conjunction with the three PWM
enable bits (PWMEN<3:1>) located in the PWMCON1
SFR. The Configuration bits and PWM enable bits
ensure that the PWM pins are in the correct states after
a device Reset occurs. The PWMPIN configuration
fuse allows the PWM module outputs to be optionally
enabled on a device Reset. If PWMPIN = 0, the PWM
outputs will be driven to their inactive states at Reset. If
PWMPIN = 1 (default), the PWM outputs will be
tri-stated. The HPOL bit specifies the polarity for the
PWMxH outputs, whereas the LPOL bit specifies the
polarity for the PWMxL outputs.
14.11.1
The PENxH and PENxL control bits in the PWMCON1
SFR enable each high PWM output pin and each low
PWM output pin, respectively. If a particular PWM
output pin not enabled, it is treated as a general
purpose I/O pin.
14.12 PWM FLTA Pin
There is one Fault input pin (FLTA) associated with the
PWM module. When asserted, this pin can optionally
drive each of the PWM I/O pins to a defined state.
14.12.1
The FLTACON SFR has 4 control bits that determine
whether a particular pair of PWM I/O pins is to be
controlled by the FLTA input pin. To enable a specific
PWM I/O pin pair for FLTA overrides, the corresponding
bit should be set in the FLTACON register.
If all enable bits are cleared in the FLTACON register,
then the FLTA input pin has no effect on the PWM
module and the pin may be used as a general purpose
interrupt or I/O pin.
DS70118H-page 90
Note:
OUTPUT PIN CONTROL
FAULT PIN ENABLE BITS
The
independent of the PWM logic. If all the
enable bits in the FLTACON register are
cleared, then the FLTA pin could be used
as a general purpose interrupt pin. The
FLTA pin has an interrupt vector, interrupt
flag bit and interrupt priority bits associ-
ated with it.
FLTA
pin
logic
can
operate
14.12.2
The FLTACON special function register has eight bits
that determine the state of each PWM I/O pin when it is
overridden by a FLTA input. When these bits are
cleared, the PWM I/O pin is driven to the inactive state.
If the bit is set, the PWM I/O pin will be driven to the
active state. The active and inactive states are
referenced to the polarity defined for each PWM I/O pin
(HPOL and LPOL polarity control bits).
14.12.3
The FLTA input pin has two modes of operation:
• Latched Mode: When the FLTA pin is driven low,
• Cycle-by-Cycle Mode: When the FLTA input pin
The Operating mode for the FLTA input pin is selected
using the FLTAM control bit in the FLTACON Special
Function Register.
The FLTA pin can be controlled manually in software.
14.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four duty cycle registers and the time base
period register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
The PWM update lockout feature is enabled by setting
the UDIS control bit in the PWMCON2 SFR. The UDIS
bit affects all duty cycle buffer registers and the PWM
time base period buffer, PTPER. No duty cycle
changes or period value changes will have effect while
UDIS = 1.
the PWM outputs will go to the states defined in
the FLTACON register. The PWM outputs will
remain in this state until the FLTA pin is driven
high and the corresponding interrupt flag has
been cleared in software. When both of these
actions have occurred, the PWM outputs will
return to normal operation at the beginning of the
next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the FLTA condition
ends, the PWM module will wait until the FLTA pin
is no longer asserted to restore the outputs.
is driven low, the PWM outputs remain in the
defined FLTA states for as long as the FLTA pin is
held low. After the FLTA pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle or
half-cycle boundary.
FAULT STATES
FAULT INPUT MODES
© 2008 Microchip Technology Inc.