DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 79

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

13.3
There are two Measurement modes which are
supported and are termed x2 and x4. These modes are
selected by the QEIM<2:0> mode select bits located in
SFR QEICON<10:8>.
When control bits QEIM<2:0> = 100 or 101, the x2
Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
increment rate. Every rising and falling edge of the
Phase A signal causes the position counter to be
incremented or decremented. The Phase B signal is
still utilized for the determination of the counter
direction, just as in the x4 mode.
Within the x2 Measurement mode, there are two
variations of how the position counter is reset:
1.
2.
When control bits QEIM<2:0> = 110 or 111, the x4
Measurement mode is selected and the QEI logic looks
at both edges of the Phase A and Phase B input
signals. Every edge of both signals causes the position
counter to increment or decrement.
Within the x4 Measurement mode, there are two
variations of how the position counter is reset:
1.
2.
The x4 Measurement mode provides for finer resolu-
tion data (more position counts) for determining motor
position.
13.4
The digital noise filter section is responsible for reject-
ing noise on the incoming capture or quadrature sig-
nals. Schmitt Trigger inputs and a three-clock cycle
delay filter combine to reject low level noise and large,
short duration noise spikes that typically occur in noise
prone applications, such as a motor system.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been
registered for three consecutive clock cycles.
For the QEA, QEB and INDX pins, the clock divide fre-
quency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>) and are derived from
the base instruction cycle T
To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for
all channels is disabled on POR and BOR.
© 2008 Microchip Technology Inc.
Position counter reset by detection of index
pulse, QEIM<2:0> = 100.
Position counter reset by match with MAXCNT,
QEIM<2:0> = 101.
Position counter reset by detection of index
pulse, QEIM<2:0> = 110.
Position counter reset by match with MAXCNT,
QEIM<2:0> = 111.
Position Measurement Mode
Programmable Digital Noise
Filters
CY
.
13.5
When the QEI module is not configured for the QEI
mode QEIM<2:0> = 001, the module can be configured
as a simple 16-bit timer/counter. The setup and control
of the auxiliary timer is accomplished through the
QEICON SFR register. This timer functions identically
to Timer1. The QEA pin is used as the timer clock input.
When configured as a timer, the POSCNT register
serves as the Timer Count Register and the MAXCNT
register serves as the Period Register. When a
timer/period register match occur, the QEI interrupt flag
will be asserted.
The only exception between the general purpose
timers and this timer is the added feature of external
Up/Down input select. When the UPDN pin is asserted
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.
The UPDN control/status bit (QEICON<11>) can be
used to select the count direction state of the Timer
register. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.
In addition, control bit UPDN_SRC (QEICON<0>)
determines whether the timer count direction state is
based on the logic state, written into the UPDN con-
trol/status bit (QEICON<11>), or the QEB pin state.
When UPDN_SRC = 1, the timer count direction is con-
trolled from the QEB pin. Likewise, when UPDN_SRC
= 0, the timer count direction is controlled by the UPDN
bit.
13.6
13.6.1
The QEI module will be halted during the CPU Sleep
mode.
13.6.2
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
Note:
Note:
Alternate 16-bit Timer/Counter
QEI Module Operation During CPU
Sleep Mode
Changing the Operational mode (i.e., from
QEI to Timer or vice versa), will not affect
the Timer/Position Count Register
contents.
This Timer does not support the External
Asynchronous Counter mode of operation.
If using an external clock source, the clock
will automatically be synchronized to the
internal instruction cycle.
QEI OPERATION DURING CPU
SLEEP MODE
TIMER OPERATION DURING CPU
SLEEP MODE
dsPIC30F2010
DS70118H-page 79