DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 133

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

19.4
19.4.1
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free running timer, which
runs off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer will continue to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
19.4.2
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer.
The enabling is done when programming the device.
By default, after chip-erase, FWDTEN bit = 1. Any
device
dsPIC30F devices allows programming of this and
other Configuration bits.
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device will
wake-up. The WDTO bit in the RCON register will be
cleared to indicate a wake-up resulting from a WDT
time-out.
Setting FWDTEN = 0 allows user software to
enable/disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
19.5
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV.
These are: Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
19.5.1
In Sleep mode, the clock to the CPU and peripherals is
shutdown. If an on-chip oscillator is being used, it is
shutdown.
The fail-safe clock monitor is not functional during
Sleep, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
The Brown-out protection circuit and the Low Voltage
Detect circuit, if enabled, will remain functional during
Sleep.
© 2008 Microchip Technology Inc.
Power-Saving Modes
programmer
Watchdog Timer (WDT)
WATCHDOG TIMER OPERATION
ENABLING AND DISABLING THE
WDT
SLEEP MODE
capable
of
programming
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• any interrupt that is individually enabled and meets
• any Reset (POR, BOR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor will restart
the same clock that was active prior to entry into Sleep
mode. When clock switching is enabled, bits
COSC<1:0> will determine the oscillator source that will
be used on wake-up. If clock switch is disabled, then
there is only one system clock.
If the clock source is an oscillator, the clock to the device
will be held off until OST times out (indicating a stable
oscillator). If PLL is used, the system clock is held off
until LOCK = 1 (indicating that the PLL is stable). In either
case, T
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of T
delay possible on wake-up from Sleep.
Moreover, if LP oscillator was active during Sleep, and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to T
delay are not applied. In order to have the smallest pos-
sible start-up delay when waking up from Sleep, one of
these faster wake-up options should be selected before
entering Sleep.
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The
processor will process the interrupt and branch to the
ISR. The Sleep status bit in RCON register is set upon
wake-up.
the required priority level
Note:
Note:
POR
POR
, T
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<1:0>
and FPR<3:0> Configuration bits.
In spite of various delays applied (T
T
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency
crystals. In such cases), if FSCM is
enabled, then the device will detect this as
a clock failure and process the clock
failure trap, the FRC oscillator will be
enabled, and the user will have to
re-enable the crystal oscillator. If FSCM is
not enabled, then the device will simply
suspend execution of code until the clock
is stable, and will remain in Sleep until the
oscillator clock has started.
LOCK
LOCK
(~ 10 μs) is applied. This is the smallest
dsPIC30F2010
and T
and T
POR
PWRT
PWRT
. PWRT delay and OST timer
), the crystal oscillator
delays are applied.
DS70118H-page 133
POR
,