DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet
DSPIC30F2010-30I/SO
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DSPIC30F2010-30I/SO Summary of contents
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... Microchip Technology Inc. dsPIC30F2010 High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70118J ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Single-cycle Multiply-Accumulate (MAC) operation • 40-stage Barrel Shifter • Dual data fetch © 2011 Microchip Technology Inc. PIC30F2010 ds Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Program Device Pins Mem. Bytes/ Instructions dsPIC30F2010 28 12K/4K DS70118J-page 4 CMOS Technology: • Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • ...
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... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2011 Microchip Technology Inc. MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 6 23 PWM3L/RE4 PWM3H/RE5 OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 FLTA/INT0/SCK1/OCFA/RE8 EMUC2/OC1/IC1/INT1/RD0 1 21 PWM2L/RE2 2 20 PWM2H/RE3 3 19 PWM3L/RE4 dsPIC30F2010 4 18 PWM3H/RE5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 dsPIC30F2010 externally. SS DS70118J-page 5 ...
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... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU Architecture Overview........................................................................................................................................................ 11 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Address Generator Units ............................................................................................................................................................ 31 5.0 Interrupts .................................................................................................................................................................................... 37 6.0 Flash Program Memory .............................................................................................................................................................. 43 7.0 Data EEPROM Memory ............................................................................................................................................................. 49 8.0 I/O Ports ..................................................................................................................................................................................... 53 9.0 Timer1 Module ........................................................................................................................................................................... 57 10.0 Timer2/3 Module ........................................................................................................................................................................ 61 11.0 Input Capture Module................................................................................................................................................................. 67 12.0 Output Compare Module ............................................................................................................................................................ 71 13 ...
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... This document contains device specific information for the dsPIC30F2010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance microcontroller (MCU) architecture. Figure 1-1 device block diagram for the dsPIC30F2010 device. © 2011 Microchip Technology Inc. dsPIC30F2010 Manual” 16-bit shows a DS70118J-page 7 ...
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... FIGURE 1-1: dsPIC30F2010 BLOCK DIAGRAM Y Data Bus Interrupt PSV and Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Loop Address Latch Control Control Logic Logic Program Memory (12 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
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... ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin. Capture inputs. The dsPIC30F2010 has four capture inputs. The inputs are numbered for consistency with the inputs on larger device variants. Quadrature Encoder Index Pulse input. ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type PGD I/O ST PGC I ST RB0-RB5 I/O ST RC13-RC14 I/O ST RD0-RD1 I/O ST RE0-RE5, I/O ST RE8 RF2, RF3 I/O ST PORTF is a bidirectional I/O port. SCK1 I/O ST SDI1 I ST SDO1 O — SS1 ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2011 Microchip Technology Inc. dsPIC30F2010 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. ...
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... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists 16-bit working registers (W0 through W15 40-bit accumulators (ACCA and ACCB), STATUS Register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Coun- ter (PC) ...
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... DCOUNT 0 DOSTART DOEND 15 0 CORCON DC IPL2 IPL1 IPL0 SRL dsPIC30F2010 PUSH.S Shadow DO Shadow Legend Working Registers Stack Pointer Limit Register AD0 Program Counter REPEAT Loop Counter DO Loop Counter DO Loop Start Address DO Loop End Address Core Configuration Register Z C STATUS Register ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: • DIVF – 16/16 signed fractional divide • ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2011 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array dsPIC30F2010 Round u r Logic Zero Backfill DS70118J-page 15 ...
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... MULTIPLIER The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2011 Microchip Technology Inc. dsPIC30F2010 2.4.2.2 Accumulator ‘Write-Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... Microchip Technology Inc. FIGURE 3-1: Manual” Figure 3-1 is dsPIC30F2010 PROGRAM SPACE MEMORY MAP FOR dsPIC30F2010 Reset - GOTO Instruction 000000 Reset - Target Address 000002 Reserved 000004 Ext. Osc. Fail Trap Address Error Trap Stack Error Trap Arithmetic Warn ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Type Instruction Access User User (TBLPAG<7> TBLRD/TBLWT Configuration (TBLPAG<7> TBLRD/TBLWT Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space Visibility Using ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’) © 2011 Microchip Technology Inc. dsPIC30F2010 A set of Table Instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the least significant word of the program address; ...
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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2011 Microchip Technology Inc. dsPIC30F2010 Program Space 0x0000 (1) PSVPAG 0x00 8 ...
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... FIGURE 3-6: DATA SPACE MEMORY MAP MSB Address 0x0001 SFR Space (See Note) 0x07FF 0x0801 512 bytes 0x08FF 0x0901 SRAM Space 0x09FF 0x8001 Optionally Mapped into Program Memory 0xFFFF Note: Unimplemented SFR or SRAM locations read as ‘0’. DS70118J-page 24 16 bits ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR Space (Y Space) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2011 Microchip Technology Inc. dsPIC30F2010 SFR Space Unused Y Space Unused Unused MAC Class Ops Read-Only Indirect EA using W8, W9 ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2011 Microchip Technology Inc. dsPIC30F2010 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70118J-page 30 © 2011 Microchip Technology Inc. ...
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... The contents of Wn forms the Effective Address (EA). The contents of Wn forms the EA post-modified (incremented or decremented constant value pre-modified (incremented or decremented signed constant value to form the EA. The sum of Wn and Wb forms the EA. The sum of Wn and a literal forms the EA. dsPIC30F2010 Table 4-1 form the basis of DS70118J-page 31 ...
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... MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 where Operand 1 is always a working register (i.e., the Addressing mode can only be register direct), which is referred to as Wb. Operand 2 can register, fetched from data memory, or 5-bit literal. The result location can be either a W register or an address location ...
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... Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2011 Microchip Technology Inc. dsPIC30F2010 4.2.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and an end address be specified and loaded ...
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... FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words DS70118J-page 34 MOV #0x1100,W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address MOV #0x8001,W0 MOV W0,MODCON ...
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... XBREV register should not be immediately followed Bit-Reversed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer dsPIC30F2010 N bytes, should not be enabled Bit Locations Swapped Left-to-Right Around Center of Binary Value DS70118J-page 35 ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F2010 device. DS70118J-page 36 Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... MCU and DSC Pro- grammer’s Reference (DS70157). The dsPIC30F2010 has 24 interrupt sources and four processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vec- tor Table (IVT) and transferring the address contained in the interrupt vector to the program counter ...
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... For example, the PLVD (Low- Voltage Detect) can be given a priority of 7. The INT0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. DS70118J-page 38 TABLE 5-1: dsPIC30F2010 INTERRUPT VECTOR TABLE INT Vector Interrupt Source Number ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2011 Microchip Technology Inc. dsPIC30F2010 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from an unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. Note: ...
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... At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine needed to process the interrupt request. dsPIC30F2010 5-1. Access to the Alternate Vector DS70118J-page 41 ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. dsPIC30F2010 Master Clear (MCLR). This allows customers to manu- facture boards with unprogrammed devices, and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2011 Microchip Technology Inc. dsPIC30F2010 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70118J-page 48 © 2011 Microchip Technology Inc. ...
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... A TBLRD instruction reads a word at the current pro- gram word address. This example uses pointer to data EEPROM. The result is placed in register W4, as shown in EXAMPLE 7-1: MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , TBLRDL [ dsPIC30F2010 Example 7-1. DATA EEPROM READ ; Init Pointer ; read data EEPROM DS70118J-page 49 ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the WR and WREN bits in NVMCON register. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2011 Microchip Technology Inc. dsPIC30F2010 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...
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... I/O cell (pad) to which they are connected. formats of the registers for the shared ports, PORTB through PORTF. Output Multiplexers 1 Output Enable 0 1 Output Data dsPIC30F2010 Figure 8-1 shows how ports are shared Table 8-1 shows the I/O Cell I/O Pad Input Data DS70118J-page 53 ...
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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...
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... TABLE 8-1: dsPIC30F2010 PORT REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — ...
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... NOTES: DS70118J-page 56 © 2011 Microchip Technology Inc. ...
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... Interrupt on 16-bit period register match or falling edge of external gate signal © 2011 Microchip Technology Inc. dsPIC30F2010 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...
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... XTAL SOSCO pF 100K © 2011 Microchip Technology Inc. dsPIC30F2010 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the period register, and is then Reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer ...
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... Idle mode, the timer will stop incrementing, unless the TSIDL (T2CON<13>) bit = ‘0’. If TSIDL = ‘1’, the timer module logic will resume the incrementing sequence upon termination of the CPU Idle mode. dsPIC30F2010 Section 9.0 for details on these two operating DS70118J-page 61 ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
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... Reset 0 T3IF Event Flag 1 TGATE See NOTE Note: The dsPIC30F2010 does not have an external pin input to TIMER3. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2011 Microchip Technology Inc. dsPIC30F2010 PR2 TMR2 Q D TGATE ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70118J-page 66 © 2011 Microchip Technology Inc. ...
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... The dsPIC DSC devices contain up to eight capture channels, (i.e., the maximum value 8). Note: The dsPIC30F2010 device has four capture inputs – IC1, IC2, IC7 and IC8. The naming of these four capture chan- Figure 11-1 nels is intentional and preserves software compatibility with other dsPIC DSC devices ...
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... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM< ...
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... Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. © 2011 Microchip Technology Inc. dsPIC30F2010 11.2.2 INPUT CAPTURE IN CPU IDLE MODE CPU Idle mode allows input capture module operation with full functionality. In the CPU Idle mode, the interrupt mode selected by the ICI< ...
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TABLE 11-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... Note: Where ‘x’ is shown, reference is made to the registers associated with the respective Output Compare channels 1and 2. © 2011 Microchip Technology Inc. dsPIC30F2010 The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 12.2 Simple Output Compare Match Mode When control bits OCM< ...
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... The IF bit is located in the IFS0 status register, and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (T2IE or T3IE), located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation. dsPIC30F2010 DS70118J-page 73 ...
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TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — OCFRZ OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — OCFRZ OCSIDL — Legend: ...
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... Quadrature Encoder Interface block diagram. TQCKPS<1:0> TQCS QEIM<2:0> TQGATE CK Q 16-bit Up/Down Counter (POSCNT) 2 Quadrature Encoder Interface Logic Comparator/ Zero Detect 3 QEIM<2:0> Mode Select Max Count Register (MAXCNT) dsPIC30F2010 bits QEIM<2:0> (QEICON<10:8>). 2 Prescaler 1, 8, 64, 256 QEIIF Event Flag Reset Equal DS70118J-page 75 ...
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... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...
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... To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2011 Microchip Technology Inc. dsPIC30F2010 13.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode QEIM< ...
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... QEI Module Operation During CPU Idle Mode Since the QEI module can function as a quadrature encoder interface 16-bit timer, the following section describes operation of the module in both modes. 13.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI ...
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TABLE 13-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB DFLTCON 0124 — — — — — POSCNT 0126 ...
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... NOTES: DS70118J-page 80 © 2011 Microchip Technology Inc. ...
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... I/O pin. A simplified block diagram of the Motor Control PWM modules is shown in Figure 14-1. The PWM module allows several modes of operation which are beneficial for specific power control applications. © 2011 Microchip Technology Inc. dsPIC30F2010 DS70118J-page 81 ...
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... FIGURE 14-1: PWM BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 FLTACON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM Time Base Note: Details of PWM Generator 1 and 2 not shown for clarity. DS70118J-page 82 PWM Enable and Mode SFRs Dead-Time Control SFR ...
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... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2011 Microchip Technology Inc. dsPIC30F2010 14.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...
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... DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional func- tions to the user ...
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... New Duty Cycle Latched PTPER PTMR Value 0 Duty Cycle Period © 2011 Microchip Technology Inc. dsPIC30F2010 14.4 Center-Aligned PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Counting mode (see Figure 14-3). The PWM compare output is driven to the active state ...
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... DUTY CYCLE REGISTER BUFFERS The four PWM duty cycle registers are double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle, there is a duty cycle register that is accessible by the user and a second duty cycle register that holds the actual compare value used in the present PWM period ...
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... PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2011 Microchip Technology Inc. dsPIC30F2010 14.10 PWM Output Override The PWM output override bits allow the user to manu- ally drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
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... PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control: • HPOL Configuration bit • LPOL Configuration bit • PWMPIN Configuration bit These three bits in the FBORPOR Configuration regis- ter (see Section 19.6 “ ...
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... Any write to the SEVTCMP register • Any device Reset © 2011 Microchip Technology Inc. dsPIC30F2010 14.15 PWM Operation During CPU Sleep Mode The FLTA input pin has the ability to wake the CPU from Sleep mode. The PWM module generates an interrupt if the FLTA pin is driven low while in Sleep ...
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TABLE 14-1: PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA — ...
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... SCL transitions while SPI- ROV is ‘1’, effectively disabling the module until SPIx- BUF is read by user software. © 2011 Microchip Technology Inc. dsPIC30F2010 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) is moved to the receive buffer ...
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... Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit FRMEN enables framed SPI support and causes the SSx pin to perform the frame synchronization pulse (FSYNC) function. The control bit SPIFSD determines whether the SSx ...
Page 93
... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been de-asserted in the middle of a transmit/receive. © 2011 Microchip Technology Inc. dsPIC30F2010 15.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down. If ...
Page 94
TABLE 15-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, read ...
Page 95
... I2CTRN is not double-buffered. Note: Following a Restart condition in 10-bit mode, the user only needs to match the first 7-bit address. bit 7 bit 0 bit 7 bit 0 bit 8 bit 0 bit 0 bit 0 bit 9 bit 0 dsPIC30F2010 2 C MODES 2 C operation are supported: Figure 16- MODE Figure 16-1. pulse is generated. During ...
Page 96
... FIGURE 16-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70118J-page 96 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control ...
Page 97
... ACK received from the master. © 2011 Microchip Technology Inc. dsPIC30F2010 16.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 98
... MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 16.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching ...
Page 99
... SCL pin is sampled high per the I C standard, FSCK may be 100 kHz or 400 kHz. However, the user can specify any baud rate MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. EQUATION 16-1: I2CBRG 2 C bus will dsPIC30F2010 2 C I2CBRG VALUE ⎛ ⎞ ...
Page 100
... CLOCK ARBITRATION Clock arbitration occurs when the master de-asserts the SCL pin (SCL allowed to float high) during any receive, transmit or Restart/Stop condition. When the SCL pin is allowed to float high, the Baud Rate Generator is suspended from counting until the SCL pin is actually sampled high ...
Page 101
TABLE 16-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...
Page 102
... NOTES: DS70118J-page 102 © 2011 Microchip Technology Inc. ...
Page 103
... Family Reference Manual” (DS70046). This section describes the Universal Asynchronous Receiver/Transmitter Communications module. Note: Since dsPIC30F2010 devices have only one UART, all references to Ux... imply that only. FIGURE 17-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus ...
Page 104
... FIGURE 17-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Note only. DS70118J-page 104 Internal Data Bus 16 Read Write UxRXREG Low Byte ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2011 Microchip Technology Inc. dsPIC30F2010 17.3 Transmitting Data 17.3.1 TRANSMITTING IN 8-BIT DATA MODE ...
Page 106
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to the Transmit Shift register (UxTSR) ...
Page 107
... Microchip Technology Inc. dsPIC30F2010 17.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...
Page 108
... UART Operation During CPU Sleep and Idle Modes 17.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shutdown and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘ ...
Page 109
TABLE 17-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 110
... NOTES: DS70118J-page 110 © 2011 Microchip Technology Inc. ...
Page 111
... AN4 AN4 AN5 AN5 AN1 © 2011 Microchip Technology Inc. dsPIC30F2010 The ADC module has six 16-bit registers: • A/D Control Register1 (ADCON1) • A/D Control Register2 (ADCON2) • A/D Control Register3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...
Page 112
... A/D Result Buffer The module contains a 16-word dual port read-only buf- fer, called ADCBUF0 through ADCBUFF, to buffer the ADC results. The RAM is 10 bits wide, but is read into dif- ferent format 16-bit words. The contents of the sixteen ADC conversion result buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 113
... Characteristics” other operating conditions. Example 18-1 ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. EXAMPLE 18-1: (SAMC = AD ADCS<5:0> • cycles to AD Therefore, Set ADCS<5:0> Actual T wait is AD dsPIC30F2010 . The source of the A/D CONVERSION CLOCK * (0.5 * (ADCS<5:0> ADCS<5:0> – time AD = 5V) ...
Page 114
... Configuration details that are not critical to the conversion speed have been omitted. Figure 18-2 depicts the recommended circuit for the conversion rates above 500 ksps. FIGURE 18-2: ADC VOLTAGE REFERENCE SCHEMATIC 0.1 μF 0.01 μ dsPIC30F2010 DS70118J-page 114 summarizes μ μ ...
Page 115
... ANx 5.0 kΩ 4.5V -40°C to +125°C to 5.5V ANx ANx or V 5.0 kΩ 3.0V -40°C to +125°C to 5.5V ANx ANx or V dsPIC30F2010 A/D Channels Configuration REF REF CH1, CH2 or CH3 S/H ADC CH0 S REF REF CH X ADC ...
Page 116
... Msps CONFIGURATION GUIDELINE The configuration for 1 Msps operation is dependent on whether a single input pin sampled or whether multiple pins will be sampled. 18.7.1.1 Single Analog Input For conversions at 1 Msps for a single analog input, at least two sample and hold channels must be enabled. ...
Page 117
... Electrical Specifications for T requirements ≤ 250Ω Sampling Switch leakage V = 0.6V T ± 500 nA negligible if Rs ≤ 5 kΩ. PIN dsPIC30F2010 ) must be allowed to HOLD impedance (R ), the interconnect S ), and the internal sampling switch IC . The combined HOLD , is S period of sampling AD and sample time AD ≤ ...
Page 118
... Module Power-Down Modes The module has three internal power modes. When the ADON bit is ‘1’, the module is in Active mode fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings ...
Page 119
... ANx pins), may cause the input buffer to consume current that exceeds the device specifications. © 2011 Microchip Technology Inc. dsPIC30F2010 18.14 Connection Considerations The analog inputs have diodes to V protection. This requires that the analog input be between V ...
Page 120
TABLE 18-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ...
Page 121
... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2011 Microchip Technology Inc. dsPIC30F2010 19.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 122
... TABLE 19-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2 PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled ...
Page 123
... FIGURE 19-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2011 Microchip Technology Inc. dsPIC30F2010 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer Switching and Control ...
Page 124
... Oscillator Configurations 19.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> Configuration bits that select one of four oscillator groups. b) AND FPR<3:0> Configuration bits that select one of 13 oscillator choices within the primary group. ...
Page 125
... PWRT expires. Note 1: OSC2 pin function is determined by the Primary (FPR<3:0>). 2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all times. for dsPIC30F2010 FRC TUNING FRC Frequency + 10.5% + 9.0% + 7.5% + 6.0% + 4. ...
Page 126
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (Clock Switch and Monitor Selection bits) in the F Configuration register. If the FSCM function is ...
Page 127
... Reset The dsPIC30F2010 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Reset cause by trap lockup (TRAPR) h) Reset caused by illegal opcode using an ...
Page 128
... FIGURE 19-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 19-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 129
... The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2011 Microchip Technology Inc. dsPIC30F2010 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 130
... Table 19-5 shows the Reset conditions for the RCON Register. Since the control bits within the RCON regis- ter are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 19-5: ...
Page 131
... FRC oscillator will be enabled, and the user will have to re-enable the crystal oscillator. If FSCM is not enabled, then the device will simply suspend execution of code until the clock is stable, and will remain in Sleep until the oscillator clock has started. dsPIC30F2010 , T and T delays POR LOCK PWRT ...
Page 132
... All Resets will wake-up the processor from Sleep mode. Any Reset, other than POR, will set the Sleep status bit POR, the Sleep bit is cleared. If Watchdog Timer is enabled, then the processor will wake-up from Sleep mode upon WDT time-out. The Sleep and WDTO status bits are both set ...
Page 133
TABLE 19-7: SYSTEM INTEGRATION REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR BGST — OSCCON 0742 TUN3 TUN2 COSC<1:0> Legend: — = unimplemented bit Note 1: Refer to the “dsPIC30F Family ...
Page 134
... NOTES: DS70118J-page 134 © 2011 Microchip Technology Inc. ...
Page 135
... All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. dsPIC30F2010 DS70118J-page 135 ...
Page 136
... Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- ...
Page 137
... Y data space prefetch address register for DSP instructions Wy ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2011 Microchip Technology Inc. dsPIC30F2010 Description DS70118J-page 137 ...
Page 138
... TABLE 20-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 139
... DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd © 2011 Microchip Technology Inc. dsPIC30F2010 # of Description word Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set ...
Page 140
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R Ws,Wnd 38 GOTO GOTO Expr GOTO Wn 39 INC INC f INC f,WREG INC Ws,Wd 40 INC2 INC2 f INC2 f,WREG INC2 ...
Page 141
... SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd © 2011 Microchip Technology Inc. dsPIC30F2010 # of Description word Negate Accumulator WREG = Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W( Pop Shadow Registers Push f to Top-of-Stack (TOS) ...
Page 142
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 72 SUB SUB Acc SUB f SUB f,WREG SUB #lit10,Wn SUB Wb,Ws,Wd SUB Wb,#lit5,Wd 73 SUBB SUBB f SUBB f,WREG SUBB #lit10,Wn SUBB Wb,Ws,Wd SUBB Wb,#lit5,Wd 74 SUBR SUBR f SUBR f,WREG SUBR Wb,Ws,Wd ...
Page 143
... Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. dsPIC30F2010 ® DS70118J-page 143 ...
Page 144
... MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
Page 145
... In-Circuit Serial Pro- gramming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. dsPIC30F2010 ® Flash microcon- ® DSCs with the powerful, yet easy- ® ...
Page 146
... PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
Page 147
... Exposure to maximum rating conditions for extended periods may affect device reliability. © 2011 Microchip Technology Inc. (except V and MCLR) ................................................... -0. (Note 1) ......................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latch-up dsPIC30F2010 + 0.3V) DD pin, rather PP Table 22-4. DS70118J-page 147 ...
Page 148
... Symbol ∑ × DMAX Symbol θ JA θ JA θ JA θ ) numbers are achieved by package simulations. JA Max MIPS dsPIC30F2010-20E — 20 — 15 — Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +150 °C -40 — +125 ° INT I O θ ...
Page 149
... V SS 0.05 — — can be lowered without losing RAM data. dsPIC30F2010 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V — V — ...
Page 150
... TABLE 22-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter Typical Max No. (1) Operating Current ( DC31a 1.6 3 DC31b 1.6 3 DC31c 1.6 3 DC31e 3.9 7 DC31f 3.5 7 DC31g 3.4 7 DC30a 3 5 DC30b 3 5 DC30c 3 5 DC30e 6 9 DC30f 6 9 DC30g 6 9 DC23a 9 14 DC23b ...
Page 151
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2011 Microchip Technology Inc. dsPIC30F2010 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 152
... TABLE 22-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter Typical Max No. (1) Power Down Current ( DC60a 0.05 — DC60b 3 25 DC60c 20 50 DC60e 0.1 — DC60f 6 35 DC60g 40 200 DC61a 30 45 DC61b 34 51 DC61c 46 69 DC61e 35 53 DC61f 39 59 DC61g 40 60 ...
Page 153
... DD DD 2.1 — (2) 50 250 400 (2,4,5) — 0.01 ±1 — 0.50 ±1.3 — 0.05 ±5 — 0.05 ±7 dsPIC30F2010 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions SMBus disabled DD V SMBus enabled V ...
Page 154
... TABLE 22-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKO ( Osc mode) V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKO ( Osc mode) Capacitive Loading Specs (2) on Output Pins DO50 C 2 OSC2/SOSC2 pin ...
Page 155
... MIN 4.5 — 5.5 3.0 — 5.5 0.8 2 2.6 40 100 — Year Provided no other specifications — — dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — V Not in operating range 2.71 V — 4.4 V — 4.73 V — — ...
Page 156
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 22-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 22-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin ...
Page 157
... All specified values ) and high for the Q3-Q4 period (1 dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions MHz EC MHz EC with 4x PLL MHz EC with 8x PLL ...
Page 158
... TABLE 22-14: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 159
... T Operating temperature -40°C ≤ T Min Typ Max Units -50 — +50 % -60 — +60 % -70 — +70 % changes. DD dsPIC30F2010 (3) (3) (3) MIPs MIPs w PLL x8 w PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — ≤ +85°C for Industrial ≤ ...
Page 160
... FIGURE 22-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 22-2 for load conditions. TABLE 22-19: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 161
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 22-1 and Table 22-10 © 2011 Microchip Technology Inc. dsPIC30F2010 SY10 SY13 Note: Refer to Figure 22-2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 162
... FIGURE 22-6: BAND GAP START-UP TIME CHARACTERISTICS 0V Enable Band Gap (see Note) Note: Band Gap is enabled when FBORPOR<7> is set. TABLE 22-21: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 163
... Asynchronous prescaler Synchronous, Greater of: with prescaler 40)/N CY Asynchronous dsPIC30F2010 Tx20 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Typ Max Units Conditions — — ns Must also meet parameter TA15 — — ns — ...
Page 164
... TABLE 22-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment TABLE 22-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS ...
Page 165
... TQ20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. dsPIC30F2010 TQ11 TQ10 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 166
... FIGURE 22-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 22-2 TABLE 22-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
Page 167
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max Units — — — — ns dsPIC30F2010 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions — — — — DS70118J-page 167 ...
Page 168
... FIGURE 22-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS FLTA/B MP20 PWMx FIGURE 22-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS PWMx Note: Refer to Figure 22-2 TABLE 22-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. MP10 T PWM Output Fall Time ...
Page 169
... T (1) (2) Typ Max 6 T — — — — — — CY dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns — ns — ns — ns — 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) DS70118J-page 169 ...
Page 170
... FIGURE 22-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ51 Index Internal Position Counter Reset TABLE 22-31: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ50 TqIL Filter Time to Recognize Low, with Digital Filter ...
Page 171
... Data Input 20 — X Data Input 20 — X dsPIC30F2010 SP20 SP21 LSb LSb IN -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns See Note 3 — ...
Page 172
... FIGURE 22-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) SDO MSb X SP40 SDI X MSb IN SP41 Note: Refer to Figure 22-2 for load conditions. TABLE 22-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
Page 173
... X Data Input 20 — X ↓ Input 120 — X Output 10 — (3) 1.5 T +40 — CY dsPIC30F2010 SP52 LSb SP51 LSb IN -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns See Note 3 — ns See Note 3 ...
Page 174
... FIGURE 22-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 22-2 for load conditions. DS70118J-page 174 SP70 SP72 SP73 SP35 SP73 SP72 ...
Page 175
... Data Input 20 — X Data Input 20 — X ↑ input 120 — — (4) Edge 1 — — — dsPIC30F2010 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns See Note 3 — ns See Note — — — ...
Page 176
... FIGURE 22-20: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 22-2 for load conditions. 2 FIGURE 22-21: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 ...
Page 177
... C™ Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ C)” (DS70068) in the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2011 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 178
... FIGURE 22-22: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS30 SDA Start Condition 2 FIGURE 22-23: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70118J-page 178 IS33 IS11 IS10 ...
Page 179
... MHz mode 0.5 — — 400 2 C™ pins (for 1 MHz mode only). dsPIC30F2010 Units Conditions μs Device must operate at a minimum of 1.5 MHz μs Device must operate at a minimum of 10 MHz. μs — μs Device must operate at a minimum of 1 ...
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... TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol Characteristic No. AD01 AV Module V Supply DD DD AD02 AV Module V Supply SS SS AD05 V Reference Voltage High REFH AD06 V Reference Voltage Low REFL AD07 V Absolute Reference Voltage REF AD08 I Current Drain REF AD10 V -V Full-Scale Input Span ...
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... The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 3: Measurements were taken with external V © 2011 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min. ...
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... FIGURE 22-24: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution SET SAMP CLEAR SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 T SAMP DONE ADIF ADRES(0) ADRES( – Software sets ADCON. SAMP to start sampling. ...
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... Software sets ADCON. ADON to start AD operation. 2 – Sampling starts after discharge period Section 17. “10-bit A/D Converter” (DS70064) of the ”dsPIC30F Family Reference Manual” (DS70046). 3 – Convert bit 9. 4 – Convert bit 8. © 2011 Microchip Technology Inc. dsPIC30F2010 AD55 AD55 ...
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... TABLE 22-39: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. AD50 T A/D Clock Period AD AD51 t A/D Internal RC Oscillator Period RC AD55 t Conversion Time CONV AD56 F Throughput Rate CNV AD57 T Sample Time SAMP AD60 t Conversion Start from Sample PCS Trigger ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. dsPIC30F2010 Example dsPIC30F2010 e -30I/MM 3 060700U Example dsPIC30F2010-30I/SP e 0648017 3 Example dsPIC30F2010-30I/SO e 0648017 DS70118J-page 185 ...
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... D TOP VIEW A3 DS70118J-page 186 EXPOSED PAD NOTE 1 BOTTOM VIEW © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2010 DS70118J-page 187 ...
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... N NOTE DS70118J-page 188 © 2011 Microchip Technology Inc. c ...
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... D N NOTE © 2011 Microchip Technology Inc. dsPIC30F2010 α h φ β DS70118J-page 189 ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70118J-page 190 © 2011 Microchip Technology Inc. ...
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... Additional minor corrections throughout document. Revision G (December 2006) This revision includes updates to the packaging diagrams. © 2011 Microchip Technology Inc. dsPIC30F2010 Revision H (March 2008) This revision reflects these updates: • Changed the location of the input reference in the 10-bit High-Speed ADC Functional Block Diagram (see ...
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... Revision J (February 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name “High-Performance, 16-bit Added Note 1 to all QFN pin diagrams (see Digital Signal Controller” ...
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... Sequence Table (16-Entry)......................................... 36 Block Diagram PWM ........................................................................... 82 © 2011 Microchip Technology Inc. dsPIC30F2010 Block Diagrams 10-bit High Speed ADC Functional........................... 111 16-bit Timer1 Module.................................................. 58 DSP Engine ................................................................ 15 dsPIC30F2010.............................................................. 8 External Power-on Reset Circuit .............................. 129 .............................................................................. 96 Input Capture Mode.................................................... 67 Oscillator System...................................................... 123 Output Compare Mode ............................................... 71 Quadrature Encoder Interface .................................... 75 Reset System ...
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... Width ........................................................................... 26 Data EEPROM Memory ...................................................... 49 Erasing ........................................................................ 50 Erasing, Block ............................................................. 50 Erasing, Word ............................................................. 50 Protection Against Spurious Write .............................. 52 Reading....................................................................... 49 Write Verify ................................................................. 52 Writing ......................................................................... 51 Writing, Block .............................................................. 52 Writing, Word .............................................................. 51 DC Characteristics ............................................................ 148 BOR .......................................................................... 155 Brown-out Reset ....................................................... 154 I/O Pin Input Specifications ....................................... 153 I/O Pin Output Specifications .................................... 154 Idle Current (I ) ...
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... MPLAB REAL ICE In-Circuit Emulator System................. 145 MPLINK Object Linker/MPLIB Object Librarian ................ 144 O OC/PWM Module Timing Characteristics.......................... 167 Operating Current (I )..................................................... 150 DD Operating MIPS vs Voltage dsPIC30F2010 .......................................................... 148 Oscillator Configurations Fast RC (FRC) .................................................. 125 Low Power RC (LPRC) ..................................... 125 Phase Locked Loop (PLL) ................................ 125 Oscillator Configurations ................................................... 124 Fail-Safe Clock Monitor............................................. 126 Initial Clock Source Selection ...
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... Enable Bits .................................................................. 88 Fault States ................................................................. 88 Modes ......................................................................... 88 Cycle-by-Cycle.................................................... 88 Latched ............................................................... 88 PWM Operation During CPU Idle Mode.............................. 89 PWM Operation During CPU Sleep Mode .......................... 89 PWM Output and Polarity Control ....................................... 88 Output Pin Control ...................................................... 88 PWM Output Override......................................................... 87 Complementary Output Mode ..................................... 87 Synchronization .......................................................... 87 PWM Period ........................................................................ 84 PWM Special Event Trigger ................................................ 89 Postscaler ...
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... Oscillator Start-up Timer ........................................... 161 Output Compare Module........................................... 166 Power-up Timer ........................................................ 161 QEI Module External Clock................................................... 165 Index Pulse ....................................................... 170 © 2011 Microchip Technology Inc. dsPIC30F2010 Quadrature Decoder................................................. 169 Reset ........................................................................ 161 Simple OC/PWM Mode ............................................ 167 SPI Module Master Mode (CKE = 0).................................... 171 Master Mode (CKE = 1).................................... 172 Slave Mode (CKE = 0) ...
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... NOTES: DS70118J-page 198 © 2011 Microchip Technology Inc. ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com click on dsPIC30F2010 contact their distributor, DS70118J-page 199 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: dsPIC30F2010 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...