DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 191

IC DSPIC MCU/DSP 12K 28SOIC

DSPIC30F2010-30I/SO

Manufacturer Part Number
DSPIC30F2010-30I/SO
Description
IC DSPIC MCU/DSP 12K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
20
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
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APPENDIX A:
Revision F (May 2006)
Previous versions of this data sheet contained
Advance or Preliminary Information. They were
distributed with incomplete characterization data.
This revision reflects these updates:
• Supported I
• 10-bit A/D High-speed Conversion timing
• Operating Current (I
• Idle Current (I
• Power-down Current (I
• I/O pin Input specifications
• BOR voltage limits
• PLL Clock Timing specifications
• PLL Jitter specifications
• Internal RC Accuracy specifications
• Watchdog Timer time-out limits
• Additional minor corrections throughout
Revision G (December 2006)
This revision includes updates to the packaging
diagrams.
© 2011 Microchip Technology Inc.
(see
requirements (see
Speed Analog-to-Digital Converter (ADC)
Module”
(see
(see
(see
(see
(see
(see
(see
(see
(see
document.
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
16-1)
22-5)
22-6)
22-7)
22-8)
22-10)
22-14)
22-15)
22-17)
22-20)
2
C Slave addresses
IDLE
) specifications
Section 18.0 “10-bit High-
DD
REVISION HISTORY
) specifications
PD
) specifications
Revision H (March 2008)
This revision reflects these updates:
• Changed the location of the input reference in the
• Removed incorrect reference to LVDIN function
• Removed erroneous reference to use of the Fast
• Added FUSE Configuration Register (FICD)
• Electrical Specifications:
• Additional minor corrections throughout the
10-bit High-Speed ADC Functional Block Diagram
(see
on Port B (see
pin 4 of SDIP and SOIC packages and pin 1 of
QFN package (see
RC Oscillator with the PLL (see
“Phase-Locked Loop
details (see
Registers”
- Resolved TBD values for parameters DO10,
- 10-bit High-Speed ADC t
- Parameter OS65 (Internal RC Accuracy) has
- Parameter D134 (Erase/Write Cycle Time)
- Parameter DC12 (RAM Data Retention Volt-
- Removed parameters OS62 (Internal FRC
- Parameter OS63 (Internal FRC Accuracy)
- Updated Min and Max values and Conditions
document
DO16, DO20, and DO26 (see
ter (time to stabilize) has been updated from
20 µs typical to 20 µs maximum (see
Table
been expanded (see
multiple Min and Max values for different tem-
peratures
has been updated to include Min and Max
values and the Typ value has been removed
(see
age) has been updated to include a Min value
(see
Jitter) and OS64 (Internal FRC Drift) and
Note 2 from AC Characteristics (see
Table
has been expanded to reflect multiple Min
and Max values for different temperatures
(see
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for
parameter SY20 (see
Figure
Table
Table
Table
22-39)
22-17)
Section 19.6 “Device Configuration
18-1)
and
22-11)
22-4)
22-17)
dsPIC30F2010
Figure
Table
Pin
1-1), previously shown on
19-8)
(PLL)”)
Diagrams)
Table
Table
PDU
22-18) to reflect
22-20)
timing parame-
Section 19.2.4
Table
DS70118J-page 191
22-9)

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