DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 132

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

dsPIC30F2010
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the Sleep
status bit. In a POR, the Sleep bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO status bits are both set.
19.5.2
In Idle mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module,
that allows them to operate during Idle.
LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• on any interrupt that is individually enabled (IE bit
• on any Reset (POR, BOR, MCLR)
• on WDT time-out
Upon wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle status bit in
RCON register is set upon wake-up.
Any Reset, other than POR, will set the Idle status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
19.6
The Configuration bits in each device Configuration
register specify some of the device modes and are pro-
grammed by a device programmer, or by using the In-
Circuit Serial Programming (ICSP) programming capa-
bility feature of the device. Each device Configuration
register is a 24-bit register, but only the lower 16 bits of
each register are used to hold configuration data.
There are five device Configuration registers available
to the user:
1.
2.
DS70118J-page 132
is ‘1’) and meets the required priority level
FOSC (0xF80000): Oscillator Configuration
Register
FWDT (0xF80002): Watchdog Timer
Configuration Register
Device Configuration Registers
IDLE MODE
3.
4.
5.
The
automatically handled when you select the device in
your device programmer. The desired state of the
Configuration bits may be specified in the source code
(dependent on the language tool used), or through the
programming interface. After the device has been
programmed, the application software may read the
Configuration bit values through the table read
instructions. For additional information, please refer to
the programming specifications of the device.
19.7
When MPLAB
In-Circuit Debugging functionality is enabled. This
function allows simple debugging functions when used
with MPLAB IDE. When the device has this feature
enabled, some of the resources are not available for
general use. These resources include the first 80 bytes
of data RAM and two I/O pins.
One of four pairs of debug I/O pins may be selected by
the user using configuration options in MPLAB IDE.
These pin pairs are named EMUD/EMUC, EMUD1/
EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3.
In each case, the selected EMUD pin is the Emulation/
Debug Data line, and the EMUC pin is the Emulation/
Debug Clock line. These pins will interface to the
MPLAB ICD 2 module available from Microchip. The
selected pair of Debug I/O pins is used by MPLAB
ICD 2 to send commands and receive responses, as
well as to send and receive data. To use the In-Circuit
Debugger function of the device, the design must
implement ICSP connections to MCLR, V
PGC, PGD and the selected EMUDx/EMUCx pin pair.
This gives rise to two possibilities:
1.
2.
Note:
FBORPOR (0xF80004): BOR and POR
Configuration Register
FGS (0xF8000A): General Code Segment
Configuration Register
FICD (0xF8000C): Debug Configuration
Register
If EMUD/EMUC is selected as the Debug I/O pin
pair, then only a 5-pin interface is required, as
the EMUD and EMUC pin functions are multi-
plexed with the PGD and PGC pin functions in
all dsPIC30F devices.
If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/
EMUC3 is selected as the Debug I/O pin pair,
then a 7-pin interface is required, as the
EMUDx/EMUCx pin functions (x = 1, 2 or 3) are
not multiplexed with the PGD and PGC pin
functions.
placement
In-Circuit Debugger
If the code protection configuration fuse
bits (FGS<GCP> and FGS<GWRP>)
have been programmed, an erase of the
entire code-protected device is only
possible at voltages V
®
ICD 2 is selected as a Debugger, the
of
© 2011 Microchip Technology Inc.
the
Configuration
DD
≥ 4.5V.
DD
bits
, V
SS
is
,