ATMEGA8535-16PJ Atmel, ATMEGA8535-16PJ Datasheet - Page 102
![IC MCU AVR 8K 5V 16MHZ 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8535-16PJ
Manufacturer Part Number
ATMEGA8535-16PJ
Description
IC MCU AVR 8K 5V 16MHZ 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16PJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Fast PWM Mode
102
ATmega8535(L)
Figure 45. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by
either using the OCF1A or ICF1 Flag according to the register used to define the TOP
value. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing the TOP to a value close to BOTTOM when the
counter is running with a low or no prescaler value must be done with care since the
CTC mode does not have the double buffering feature. If the new value written to
OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the
Compare Match. The counter will then have to count to its maximum value (0xFFFF)
and wrap around starting at 0x0000 before the Compare Match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double
buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle
its logical level on each Compare Match by setting the compare output mode bits to tog-
gle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the
data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will
have a maximum frequency of f
waveform frequency is defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle
that the counter counts from MAX to 0x0000.
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) pro-
vides a high frequency PWM waveform generation option. The fast PWM differs from
the other PWM options by its single-slope operation. The counter counts from BOTTOM
to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC1x) is set on the Compare Match between TCNT1 and OCR1x, and
cleared at BOTTOM. In inverting Compare Output mode output is cleared on Compare
Match and set at BOTTOM. Due to the single-slope operation, the operating frequency
of the fast PWM mode can be twice as high as the phase correct and phase and fre-
quency correct PWM modes that use dual-slope operation. This high frequency makes
the fast PWM mode well suited for power regulation, rectification, and DAC applications.
TCNTn
OCnA
(Toggle)
Period
1
f
OCnA
OC
1
2
A
= f
=
clk_I/O
-------------------------------------------------- -
2 N
⋅
/2 when OCR1A is set to zero (0x0000). The
⋅
3
(
f
1
clk_I/O
+
OCRnA
4
)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnA1:0 = 1)
2502K–AVR–10/06
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